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2023-02-01 - 14:31

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Wed Feb 01, 2023 00:51:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3168199326128,2cyclictest151rcu_preempt21:21:3322
31580991741,171cyclictest0-21swapper/1521:49:227
315809916222,87cyclictest0-21swapper/1500:39:207
315959916031,111cyclictest0-21swapper/1723:55:229
315959916031,111cyclictest0-21swapper/1723:55:219
315959915741,73cyclictest0-21swapper/1723:44:199
315959915531,65cyclictest0-21swapper/1719:20:159
315959915531,65cyclictest0-21swapper/1719:20:159
315419915328,89cyclictest0-21swapper/1020:09:282
315959915028,97cyclictest0-21swapper/1723:35:149
315959915028,97cyclictest0-21swapper/1723:35:139
315959914627,80cyclictest0-21swapper/1700:10:309
315959914627,80cyclictest0-21swapper/1700:10:309
31646991420,82cyclictest0-21swapper/2400:05:0917
31646991420,82cyclictest0-21swapper/2400:05:0817
315959914020,77cyclictest0-21swapper/1722:06:489
315329914020,118cyclictest0-21swapper/900:36:3331
315329914020,118cyclictest0-21swapper/900:02:5431
315329914020,118cyclictest0-21swapper/900:02:5431
315329913920,118cyclictest0-21swapper/919:35:1731
315329913920,118cyclictest0-21swapper/919:35:1631
316089913821,69cyclictest0-21swapper/1922:04:5611
315329913821,87cyclictest0-21swapper/923:13:3031
315329913720,85cyclictest0-21swapper/923:05:4331
315329913720,85cyclictest0-21swapper/923:05:4231
315329913720,76cyclictest0-21swapper/923:20:0131
315329913720,76cyclictest0-21swapper/923:20:0131
315329913720,72cyclictest0-21swapper/921:46:3631
315329913720,72cyclictest0-21swapper/919:25:2031
315329913720,72cyclictest0-21swapper/919:25:1931
31617991360,85cyclictest0-21swapper/2021:15:0013
315419913649,52cyclictest0-21swapper/1021:53:022
31617991350,82cyclictest0-21swapper/2000:35:3113
315419913553,56cyclictest0-21swapper/1023:07:512
315419913553,56cyclictest0-21swapper/1023:07:502
315329913521,113cyclictest0-21swapper/923:30:1831
315329913521,113cyclictest0-21swapper/923:30:1731
315809913432,64cyclictest0-21swapper/1521:32:167
315419913453,58cyclictest0-21swapper/1021:12:272
315419913449,60cyclictest0-21swapper/1023:57:332
315419913449,60cyclictest0-21swapper/1023:57:332
315419913446,57cyclictest0-21swapper/1023:48:282
315419913446,57cyclictest0-21swapper/1023:48:282
315809913349,60cyclictest0-21swapper/1522:08:387
315809913340,92cyclictest0-21swapper/1521:40:187
315419913350,56cyclictest0-21swapper/1023:54:532
315419913350,56cyclictest0-21swapper/1023:54:532
315419913340,61cyclictest0-21swapper/1000:17:522
315419913340,61cyclictest0-21swapper/1000:17:522
315419913330,65cyclictest0-21swapper/1022:35:162
316819913232,32cyclictest0-21swapper/2922:44:5522
316089913226,67cyclictest0-21swapper/1923:58:4611
316089913226,67cyclictest0-21swapper/1923:58:4611
315809913271,42cyclictest0-21swapper/1500:31:187
315809913271,42cyclictest0-21swapper/1500:31:187
315419913230,69cyclictest0-21swapper/1023:29:312
315419913230,69cyclictest0-21swapper/1023:29:312
316089913148,56cyclictest0-21swapper/1920:00:2711
315959913117,85cyclictest3231-21/usr/sbin/munin22:50:209
315419913133,66cyclictest0-21swapper/1021:41:162
315419913129,70cyclictest0-21swapper/1021:47:092
315419913127,68cyclictest0-21swapper/1022:26:482
315419913126,67cyclictest0-21swapper/1022:44:202
315809913047,57cyclictest0-21swapper/1523:07:257
315809913047,57cyclictest0-21swapper/1523:07:257
315419913050,64cyclictest0-21swapper/1023:15:212
315419913050,64cyclictest0-21swapper/1023:15:202
315419913037,71cyclictest0-21swapper/1019:53:522
315419913029,63cyclictest0-21swapper/1019:31:582
315419913029,63cyclictest0-21swapper/1019:31:582
315419913025,62cyclictest0-21swapper/1022:06:572
315419913013,87cyclictest0-21swapper/1000:06:382
315419913013,87cyclictest0-21swapper/1000:06:382
316179912929,32cyclictest0-21swapper/2021:45:3113
316089912924,63cyclictest0-21swapper/1923:41:3911
315959912937,63cyclictest0-21swapper/1719:45:279
315959912937,63cyclictest0-21swapper/1719:45:269
315809912947,57cyclictest0-21swapper/1522:34:167
315419912928,70cyclictest0-21swapper/1022:24:342
315419912928,66cyclictest0-21swapper/1019:25:012
315419912928,66cyclictest0-21swapper/1019:25:012
315419912927,68cyclictest0-21swapper/1020:55:192
315419912926,67cyclictest0-21swapper/1020:40:212
315329912920,23cyclictest0-21swapper/920:47:1731
316179912832,72cyclictest0-21swapper/2000:21:3513
316179912832,72cyclictest0-21swapper/2000:21:3513
316089912846,52cyclictest0-21swapper/1921:50:3111
316089912839,60cyclictest0-21swapper/1919:30:3211
316089912839,60cyclictest0-21swapper/1919:30:3111
316089912818,74cyclictest0-21swapper/1900:18:3311
316089912818,74cyclictest0-21swapper/1900:18:3311
31603991280,80cyclictest0-21swapper/1819:45:2910
31603991280,80cyclictest0-21swapper/1819:45:2810
315959912827,62cyclictest0-21swapper/1723:22:479
315959912827,62cyclictest0-21swapper/1723:22:479
315809912843,54cyclictest0-21swapper/1522:10:457
315809912837,59cyclictest0-21swapper/1523:55:317
315809912837,59cyclictest0-21swapper/1523:55:307
315419912886,41cyclictest0-21swapper/1000:10:562
315419912886,41cyclictest0-21swapper/1000:10:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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