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2022-09-30 - 15:41
/usr/bin/Xorg /usr/bin/Xorg

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Fri Sep 30, 2022 12:48:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1507999317116,1cyclictest143-21ksoftirqd/2111:04:0214
2279912100,202ptp4l0-21swapper/107:08:401
150469916929,98cyclictest0-21swapper/1712:30:029
1507999164162,1cyclictest143-21ksoftirqd/2112:27:2714
15079991608,149cyclictest0-21swapper/2110:22:2414
15079991608,116cyclictest0-21swapper/2109:40:3714
15079991598,145cyclictest0-21swapper/2111:26:0014
15079991588,90cyclictest0-21swapper/2110:43:4714
151159915614,80cyclictest0-21swapper/2910:36:5822
15079991568,144cyclictest0-21swapper/2109:57:0214
15094991460,92cyclictest0-21swapper/2408:03:5017
14945991460,88cyclictest0-21swapper/212:32:2712
15046991430,86cyclictest0-21swapper/1711:44:389
14986991430,85cyclictest0-21swapper/707:20:3029
150469914250,58cyclictest0-21swapper/1710:17:479
149619914260,36cyclictest151rcu_preempt12:37:3826
150469914151,60cyclictest0-21swapper/1708:46:419
150469914151,60cyclictest0-21swapper/1708:46:419
150469914150,55cyclictest0-21swapper/1711:08:179
150469914148,58cyclictest0-21swapper/1709:11:169
150469914148,58cyclictest0-21swapper/1709:11:159
150169914178,11cyclictest151rcu_preempt09:19:433
15046991401,87cyclictest0-21swapper/1710:37:179
15046991400,83cyclictest0-21swapper/1711:01:529
150469913947,60cyclictest0-21swapper/1709:50:159
15046991390,82cyclictest0-21swapper/1711:24:199
150469913841,60cyclictest0-21swapper/1710:05:459
150469913841,59cyclictest0-21swapper/1711:51:359
150469913831,68cyclictest0-21swapper/1712:01:439
15046991380,82cyclictest0-21swapper/1712:10:179
150469913737,63cyclictest0-21swapper/1710:40:299
150469913730,66cyclictest0-21swapper/1710:58:399
15046991370,86cyclictest0-21swapper/1710:12:109
15046991370,82cyclictest0-21swapper/1712:15:389
15046991370,77cyclictest0-21swapper/1711:16:509
149459913741,61cyclictest0-21swapper/212:29:1512
150799913623,109cyclictest143-21ksoftirqd/2112:30:2614
150469913628,68cyclictest0-21swapper/1712:26:509
150469913628,63cyclictest0-21swapper/1710:45:189
150469913526,65cyclictest0-21swapper/1712:05:299
15046991350,83cyclictest0-21swapper/1710:22:519
15046991350,81cyclictest0-21swapper/1709:55:049
149869913549,52cyclictest0-21swapper/710:55:0229
15099991340,81cyclictest0-21swapper/2511:30:5118
150469913454,64cyclictest0-21swapper/1711:12:009
150469913450,54cyclictest0-21swapper/1711:58:009
150469913430,65cyclictest0-21swapper/1711:35:319
150469913430,65cyclictest0-21swapper/1711:28:039
150469913430,62cyclictest0-21swapper/1710:29:169
15046991340,79cyclictest0-21swapper/1711:33:569
150169913427,64cyclictest151rcu_preempt09:10:023
150169913427,64cyclictest151rcu_preempt09:10:023
150469913330,67cyclictest0-21swapper/1708:00:129
150469913326,62cyclictest0-21swapper/1707:10:309
15046991330,80cyclictest0-21swapper/1707:50:359
149869913342,60cyclictest0-21swapper/709:26:4729
149869913342,60cyclictest0-21swapper/709:26:4729
149869913329,69cyclictest0-21swapper/710:23:1429
149869913328,68cyclictest0-21swapper/710:17:1929
149869913327,65cyclictest0-21swapper/707:15:4129
150469913253,63cyclictest0-21swapper/1709:05:239
150469913253,63cyclictest0-21swapper/1709:05:239
150469913237,68cyclictest0-21swapper/1712:22:029
150469913227,62cyclictest0-21swapper/1712:35:569
149869913238,61cyclictest0-21swapper/712:14:5529
149349913214,73cyclictest23410-21taskset08:59:290
149349913214,73cyclictest23410-21taskset08:59:290
150999913124,72cyclictest0-21swapper/2512:13:0618
15079991318,88cyclictest0-21swapper/2111:40:2514
150469913156,68cyclictest0-21swapper/1708:19:259
150469913130,62cyclictest0-21swapper/1709:33:409
149869913136,60cyclictest0-21swapper/711:48:4429
149869913128,69cyclictest0-21swapper/707:45:2029
15046991300,76cyclictest0-21swapper/1708:08:459
149869913029,68cyclictest0-21swapper/710:09:2129
149869913028,71cyclictest0-21swapper/711:15:3729
149869913027,68cyclictest0-21swapper/709:41:3329
149459913026,66cyclictest0-21swapper/210:34:3812
150999912927,59cyclictest0-21swapper/2509:43:2718
15079991298,74cyclictest0-21swapper/2110:45:5414
150469912928,62cyclictest0-21swapper/1709:44:569
15046991291,80cyclictest0-21swapper/1710:53:199
149869912930,69cyclictest0-21swapper/708:25:2429
149869912930,69cyclictest0-21swapper/708:25:2429
14961991290,64cyclictest0-21swapper/412:20:3326
150999912825,67cyclictest0-21swapper/2507:50:2718
150999912824,63cyclictest0-21swapper/2510:10:1118
150469912828,58cyclictest0-21swapper/1707:25:119
15046991280,76cyclictest0-21swapper/1710:00:249
149869912831,74cyclictest0-21swapper/709:51:5129
149869912829,67cyclictest0-21swapper/712:21:5129
149869912826,62cyclictest0-21swapper/708:11:1529
149869912825,64cyclictest0-21swapper/710:31:4729
149619912814,90cyclictest151rcu_preempt11:08:5626
149549912812,103cyclictest0-21swapper/310:04:2523
149459912828,66cyclictest0-21swapper/211:05:5412
149459912826,67cyclictest0-21swapper/211:29:5712
149459912825,59cyclictest0-21swapper/210:35:2612
150999912727,64cyclictest0-21swapper/2510:52:2318
150999912719,35cyclictest0-21swapper/2512:25:2318
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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