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2022-05-28 - 13:30

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Sat May 28, 2022 00:49:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2642912970,287ptp4l0-21swapper/119:05:161
2642912970,287ptp4l0-21swapper/119:05:151
19437991898,175cyclictest0-21swapper/2622:05:1419
19437991808,139cyclictest0-21swapper/2622:44:1419
19437991768,139cyclictest0-21swapper/2623:35:0119
19437991768,139cyclictest0-21swapper/2623:35:0019
19319991675,146cyclictest0-21swapper/922:00:0831
19437991638,94cyclictest0-21swapper/2622:53:2019
19319991565,122cyclictest0-21swapper/923:40:2431
19319991565,122cyclictest0-21swapper/923:40:2331
193779915227,91cyclictest0-21swapper/1622:36:388
193779915227,124cyclictest0-21swapper/1600:15:168
193779915227,124cyclictest0-21swapper/1600:15:158
193779915127,77cyclictest0-21swapper/1623:09:118
193779915027,74cyclictest0-21swapper/1620:05:118
193779914821,108cyclictest7945-21diskmemload21:11:408
193779914727,82cyclictest0-21swapper/1623:40:468
193779914727,82cyclictest0-21swapper/1623:40:458
193779914725,80cyclictest0-21swapper/1620:25:138
193779914721,107cyclictest0-21swapper/1623:18:378
193999914633,64cyclictest0-21swapper/1922:36:0611
19437991458,110cyclictest0-21swapper/2623:24:1919
193779914526,96cyclictest0-21swapper/1623:28:588
193779914520,90cyclictest0-21swapper/1621:05:188
193779914519,125cyclictest0-21swapper/1622:31:388
194379914421,91cyclictest0-21swapper/2621:05:2219
19437991441,83cyclictest0-21swapper/2600:12:2519
19437991441,83cyclictest0-21swapper/2600:12:2519
193779914419,96cyclictest0-21swapper/1600:32:348
193779914419,96cyclictest0-21swapper/1600:32:338
19437991430,87cyclictest0-21swapper/2623:15:1419
193999914329,113cyclictest0-21swapper/1923:04:2711
193779914217,117cyclictest0-21swapper/1622:28:228
19280991420,88cyclictest0-21swapper/200:34:2912
19280991420,88cyclictest0-21swapper/200:34:2812
19442991401,137cyclictest0-21swapper/2723:11:3020
19386991380,81cyclictest0-21swapper/1722:29:079
19360991380,86cyclictest0-21swapper/1422:42:266
19319991385,81cyclictest0-21swapper/922:51:5831
194379913722,105cyclictest0-21swapper/2622:48:3119
193609913718,90cyclictest0-21swapper/1423:41:136
193609913718,90cyclictest0-21swapper/1423:41:136
193049913753,57cyclictest0-21swapper/623:46:2628
193049913725,76cyclictest0-21swapper/622:39:3828
193779913627,49cyclictest0-21swapper/1620:40:378
193049913648,54cyclictest0-21swapper/622:57:4828
192809913650,61cyclictest0-21swapper/221:00:4212
192809913650,56cyclictest0-21swapper/221:30:5312
193049913546,59cyclictest0-21swapper/620:55:1328
192809913547,52cyclictest0-21swapper/221:18:2012
193869913466,67cyclictest0-21swapper/1723:48:149
193049913442,57cyclictest0-21swapper/619:16:3328
193049913429,63cyclictest0-21swapper/622:25:1228
192809913445,58cyclictest0-21swapper/222:05:5412
193609913321,110cyclictest0-21swapper/1422:51:326
193049913328,70cyclictest0-21swapper/622:15:1828
193049913328,69cyclictest0-21swapper/623:00:1428
192809913348,58cyclictest0-21swapper/223:35:4112
192809913334,66cyclictest0-21swapper/221:47:4412
193529913256,39cyclictest0-21swapper/1322:50:275
193199913230,60cyclictest0-21swapper/922:22:0231
193049913239,61cyclictest0-21swapper/600:20:3928
193049913239,61cyclictest0-21swapper/600:20:3828
193049913238,62cyclictest0-21swapper/623:11:0928
193049913230,70cyclictest0-21swapper/619:32:1428
193049913228,69cyclictest0-21swapper/621:20:0228
192809913226,64cyclictest0-21swapper/200:38:1312
192809913226,64cyclictest0-21swapper/200:38:1312
193779913124,72cyclictest0-21swapper/1600:06:118
193779913124,72cyclictest0-21swapper/1600:06:108
19360991310,80cyclictest0-21swapper/1400:18:386
19360991310,80cyclictest0-21swapper/1400:18:386
193049913131,66cyclictest0-21swapper/621:53:0828
193049913130,71cyclictest0-21swapper/620:40:5928
193049913130,68cyclictest0-21swapper/600:09:2528
193049913130,68cyclictest0-21swapper/600:09:2528
193049913128,67cyclictest0-21swapper/620:40:0128
193049913128,66cyclictest0-21swapper/620:06:1728
193049913127,72cyclictest0-21swapper/620:46:3028
193049913127,70cyclictest0-21swapper/623:35:3028
193049913127,70cyclictest0-21swapper/600:29:4328
193049913127,70cyclictest0-21swapper/600:29:4328
193049913127,67cyclictest0-21swapper/621:46:4428
193049913126,61cyclictest0-21swapper/621:35:3028
192809913130,68cyclictest0-21swapper/221:10:5212
192809913128,69cyclictest0-21swapper/223:11:0012
192809913127,65cyclictest0-21swapper/222:20:5212
192809913126,65cyclictest0-21swapper/220:15:1712
192809913126,64cyclictest0-21swapper/219:13:5012
192809913125,60cyclictest0-21swapper/219:54:2712
193999913027,69cyclictest0-21swapper/1923:37:0111
193869913062,67cyclictest0-21swapper/1723:15:069
193609913022,37cyclictest0-21swapper/1420:36:526
193199913021,94cyclictest0-21swapper/921:40:2831
193049913038,63cyclictest0-21swapper/619:45:2828
193049913028,72cyclictest0-21swapper/623:42:0928
193049913028,72cyclictest0-21swapper/623:42:0928
193049913028,67cyclictest0-21swapper/622:05:5728
193049913028,67cyclictest0-21swapper/621:13:0428
193049913027,68cyclictest0-21swapper/623:25:4628
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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