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2024-09-08 - 08:24

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8s.osadl.org (updated Sun Sep 08, 2024 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1139426534,16sleep30-21swapper/319:05:023
204802610,0sleep00-21swapper/019:20:200
132091610,5ptp4l0-21swapper/719:09:487
132091610,4ptp4l0-21swapper/019:05:310
132091610,30ptp4l0-21swapper/119:05:491
76902600,0sleep00-21swapper/023:35:010
132091600,5ptp4l0-21swapper/519:06:275
1310226050,6sleep20-21swapper/219:07:172
271862560,0sleep40-21swapper/422:28:474
1331525139,7sleep60-21swapper/619:09:546
132091500,2ptp4l0-21swapper/419:05:174
117862480,0sleep60-21swapper/622:53:256
132091310,3ptp4l0-21swapper/122:00:011
132091310,0ptp4l10519-21ps00:25:195
132091310,0ptp4l0-21swapper/521:05:195
132091310,0ptp4l0-21swapper/500:30:155
132091310,0ptp4l0-21swapper/122:29:391
132091300,0ptp4l0-21swapper/523:14:295
132091300,0ptp4l0-21swapper/521:55:155
132091300,0ptp4l0-21swapper/521:54:015
132091300,0ptp4l0-21swapper/519:37:385
132091300,0ptp4l0-21swapper/400:34:564
132091300,0ptp4l0-21swapper/123:45:201
132091300,0ptp4l0-21swapper/100:40:011
132091290,4ptp4l18849-21ssh23:04:231
132091290,0ptp4l0-21swapper/522:31:115
132091290,0ptp4l0-21swapper/522:28:215
132091290,0ptp4l0-21swapper/522:06:025
132091290,0ptp4l0-21swapper/520:55:155
132091290,0ptp4l0-21swapper/500:23:435
132091290,0ptp4l0-21swapper/221:22:012
132091280,6ptp4l0-21swapper/523:26:115
132091280,0ptp4l0-21swapper/621:32:546
132091280,0ptp4l0-21swapper/523:02:035
132091280,0ptp4l0-21swapper/522:24:565
132091280,0ptp4l0-21swapper/521:49:275
132091280,0ptp4l0-21swapper/423:47:544
132091280,0ptp4l0-21swapper/221:32:252
132091280,0ptp4l0-21swapper/123:12:531
132091280,0ptp4l0-21swapper/119:35:231
132091280,0ptp4l0-21swapper/100:13:291
132091280,0ptp4l0-21swapper/100:07:261
132091270,1ptp4l22681-21latency_hist23:10:015
132091270,0ptp4l0-21swapper/723:29:247
132091270,0ptp4l0-21swapper/722:58:097
132091270,0ptp4l0-21swapper/722:54:247
132091270,0ptp4l0-21swapper/523:50:135
132091270,0ptp4l0-21swapper/523:49:205
132091270,0ptp4l0-21swapper/523:33:295
132091270,0ptp4l0-21swapper/521:39:485
132091270,0ptp4l0-21swapper/521:14:595
132091270,0ptp4l0-21swapper/123:51:001
132091270,0ptp4l0-21swapper/122:14:261
132091260,1ptp4l3251-21irqrtprio21:05:151
132091260,0ptp4l0-21swapper/623:38:486
132091260,0ptp4l0-21swapper/622:43:186
132091260,0ptp4l0-21swapper/523:20:325
132091260,0ptp4l0-21swapper/522:18:425
132091260,0ptp4l0-21swapper/500:37:385
132091260,0ptp4l0-21swapper/222:08:032
132091260,0ptp4l0-21swapper/122:34:121
132091260,0ptp4l0-21swapper/121:53:241
132091260,0ptp4l0-21swapper/121:46:161
132091260,0ptp4l0-21swapper/119:20:201
132091260,0ptp4l0-21swapper/100:33:571
132091250,0ptp4l0-21swapper/719:48:427
132091250,0ptp4l0-21swapper/700:18:347
132091250,0ptp4l0-21swapper/623:57:576
132091250,0ptp4l0-21swapper/523:40:395
132091250,0ptp4l0-21swapper/523:40:385
132091250,0ptp4l0-21swapper/521:22:375
132091250,0ptp4l0-21swapper/521:17:265
132091250,0ptp4l0-21swapper/519:55:185
132091250,0ptp4l0-21swapper/519:23:275
132091250,0ptp4l0-21swapper/500:09:405
132091250,0ptp4l0-21swapper/423:41:194
132091250,0ptp4l0-21swapper/423:41:184
132091250,0ptp4l0-21swapper/222:50:342
132091250,0ptp4l0-21swapper/222:16:412
132091250,0ptp4l0-21swapper/123:41:401
132091250,0ptp4l0-21swapper/123:41:391
132091250,0ptp4l0-21swapper/123:19:311
132091250,0ptp4l0-21swapper/122:44:111
132091250,0ptp4l0-21swapper/122:21:081
132091250,0ptp4l0-21swapper/121:55:181
132091250,0ptp4l0-21swapper/121:30:131
132091250,0ptp4l0-21swapper/119:14:321
132091240,3ptp4l0-21swapper/323:29:083
132091240,3ptp4l0-21swapper/100:15:481
132091240,2ptp4l6579-21sort22:45:151
132091240,1ptp4l9876-21expr20:10:115
132091240,1ptp4l26385-21users00:00:206
132091240,1ptp4l23735-21smart_sda21:35:202
132091240,1ptp4l16839-21cpuspeed_turbos20:25:115
132091240,1ptp4l1056-21latency21:00:171
132091240,1ptp4l1056-21latency21:00:161
132091240,0ptp4l0-21swapper/722:09:187
132091240,0ptp4l0-21swapper/720:35:167
132091240,0ptp4l0-21swapper/720:20:217
132091240,0ptp4l0-21swapper/623:45:396
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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