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2023-02-07 - 18:50

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rackcslot8.osadl.org (updated Tue Feb 07, 2023 12:50:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2471099321122,196cyclictest151rcu_preempt10:28:068
2471099321122,196cyclictest151rcu_preempt10:28:068
2279912790,264ptp4l0-21swapper/107:10:001
2279912790,264ptp4l0-21swapper/107:10:001
231191199194,4phc2sys0-21swapper/207:09:2512
231191199194,4phc2sys0-21swapper/207:09:2512
247299915834,80cyclictest0-21swapper/2111:11:3514
247299915431,85cyclictest0-21swapper/2108:55:2414
247299915429,101cyclictest0-21swapper/2111:53:5414
247299915429,101cyclictest0-21swapper/2111:53:5414
247299915128,86cyclictest0-21swapper/2109:35:2914
247299914926,79cyclictest0-21swapper/2111:30:5514
247299914926,79cyclictest0-21swapper/2111:30:5414
246429914616,129cyclictest0-21swapper/310:53:1223
246429914616,129cyclictest0-21swapper/310:53:1223
24729991450,85cyclictest0-21swapper/2107:57:4214
24642991440,86cyclictest0-21swapper/311:42:5423
24642991440,86cyclictest0-21swapper/311:42:5423
24642991440,84cyclictest0-21swapper/312:35:1723
24642991440,84cyclictest0-21swapper/312:35:1623
246939914358,57cyclictest0-21swapper/1210:50:294
246939914358,57cyclictest0-21swapper/1210:50:294
24636991430,84cyclictest0-21swapper/210:52:2112
24636991430,84cyclictest0-21swapper/210:52:2012
247299914228,69cyclictest0-21swapper/2112:31:4514
24636991410,85cyclictest0-21swapper/209:37:0012
247669914034,51cyclictest0-21swapper/2710:10:1820
247449914035,56cyclictest0-21swapper/2411:16:5117
24636991400,83cyclictest0-21swapper/209:46:0512
24636991400,81cyclictest0-21swapper/212:00:1312
24636991400,81cyclictest0-21swapper/212:00:1312
24636991400,81cyclictest0-21swapper/208:01:2112
24766991390,85cyclictest0-21swapper/2708:54:1520
246939913929,70cyclictest0-21swapper/1209:42:034
24636991390,84cyclictest0-21swapper/212:36:5112
24636991390,84cyclictest0-21swapper/212:36:5112
24636991390,82cyclictest0-21swapper/212:21:2112
24636991390,82cyclictest0-21swapper/212:21:2112
24636991390,82cyclictest0-21swapper/210:01:0312
24636991390,82cyclictest0-21swapper/209:28:2712
24642991380,85cyclictest0-21swapper/312:13:5223
24642991380,85cyclictest0-21swapper/312:13:5223
24636991380,86cyclictest0-21swapper/212:09:0512
24636991380,86cyclictest0-21swapper/212:09:0512
24636991380,82cyclictest0-21swapper/211:43:5712
24636991380,82cyclictest0-21swapper/211:43:5612
24636991380,82cyclictest0-21swapper/211:20:4112
24636991380,80cyclictest0-21swapper/209:15:2312
24729991370,83cyclictest0-21swapper/2108:45:0114
246939913730,65cyclictest0-21swapper/1212:22:064
246939913730,65cyclictest0-21swapper/1212:22:064
24636991370,80cyclictest0-21swapper/208:05:3712
24636991360,80cyclictest0-21swapper/209:10:1712
24792991350,76cyclictest0-21swapper/3110:56:0625
246939913530,63cyclictest0-21swapper/1207:47:124
246369913537,61cyclictest0-21swapper/210:17:4112
24636991350,82cyclictest0-21swapper/212:12:1712
24636991350,82cyclictest0-21swapper/212:12:1612
24636991350,79cyclictest0-21swapper/211:45:3312
24636991350,79cyclictest0-21swapper/211:45:3312
24636991350,75cyclictest0-21swapper/212:30:2712
247669913449,56cyclictest0-21swapper/2712:29:3820
24744991340,78cyclictest0-21swapper/2409:30:3117
246939913429,65cyclictest0-21swapper/1211:09:574
247669913347,58cyclictest0-21swapper/2708:15:2420
247669913344,62cyclictest0-21swapper/2709:37:5720
24636991330,82cyclictest0-21swapper/209:43:1112
24636991330,78cyclictest0-21swapper/210:56:5412
247669913227,67cyclictest0-21swapper/2710:45:3520
247669913226,69cyclictest0-21swapper/2710:50:2420
247669913226,69cyclictest0-21swapper/2710:50:2420
247669913226,63cyclictest0-21swapper/2711:44:1120
247669913226,63cyclictest0-21swapper/2711:44:1120
246939913247,54cyclictest0-21swapper/1208:15:404
246939913227,64cyclictest0-21swapper/1209:25:334
246369913229,62cyclictest0-21swapper/210:22:1112
246369913227,68cyclictest0-21swapper/212:29:3812
247669913130,63cyclictest0-21swapper/2712:24:5820
247669913130,63cyclictest0-21swapper/2712:24:5820
247669913126,69cyclictest0-21swapper/2711:45:2620
247669913126,69cyclictest0-21swapper/2711:45:2620
246369913128,65cyclictest0-21swapper/211:38:3612
246369913128,65cyclictest0-21swapper/211:38:3612
247669913047,53cyclictest0-21swapper/2708:55:3020
247669913030,74cyclictest0-21swapper/2708:07:5720
247669913027,69cyclictest0-21swapper/2711:32:3720
247669913027,69cyclictest0-21swapper/2711:32:3720
247669913027,66cyclictest0-21swapper/2711:01:3720
247669913026,71cyclictest0-21swapper/2708:46:2520
247449913031,50cyclictest0-21swapper/2409:57:4617
247669912928,71cyclictest0-21swapper/2707:44:2620
247669912923,69cyclictest0-21swapper/2709:31:1820
246369912922,65cyclictest0-21swapper/210:40:5412
24636991290,80cyclictest0-21swapper/210:31:4912
24636991290,77cyclictest0-21swapper/207:55:4712
24636991290,73cyclictest0-21swapper/207:15:4212
247669912831,73cyclictest0-21swapper/2712:34:3620
247669912829,63cyclictest0-21swapper/2707:15:1920
247669912828,70cyclictest0-21swapper/2710:30:3520
246429912850,52cyclictest0-21swapper/308:12:2123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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