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2022-08-19 - 12:38

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100, highest latencies:
System rackcslot8.osadl.org (updated Fri Aug 19, 2022 00:48:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1800499357159,2cyclictest151rcu_preempt21:45:0716
1791199343145,1cyclictest151rcu_preempt22:40:3126
137192315304,8sleep270-21swapper/2719:05:1720
179889925757,3cyclictest151rcu_preempt22:52:1614
231191228219,7phc2sys0-21swapper/219:09:2012
180449921228,102cyclictest0-21swapper/2900:04:1622
1793099194193,1cyclictest0-21swapper/923:52:4331
180449918626,130cyclictest0-21swapper/2921:23:2522
180449918626,130cyclictest0-21swapper/2921:23:2522
180449918625,140cyclictest0-21swapper/2921:00:0022
180449918625,140cyclictest0-21swapper/2921:00:0022
180449918325,102cyclictest0-21swapper/2922:24:5222
180449917925,110cyclictest0-21swapper/2921:56:0222
180449917021,118cyclictest0-21swapper/2922:36:2622
179409916913,40cyclictest0-21swapper/1200:07:324
2279911580,149ptp4l0-21swapper/119:06:331
180449915825,79cyclictest0-21swapper/2921:36:4722
179409915524,42cyclictest151rcu_preempt00:03:174
1802699153149,0cyclictest173-21ksoftirqd/2623:40:1119
180449915125,80cyclictest0-21swapper/2900:26:0222
153432150142,6sleep00-21swapper/019:05:220
179409914812,85cyclictest0-21swapper/1223:21:024
180449914626,90cyclictest0-21swapper/2923:33:4922
17930991460,87cyclictest0-21swapper/920:50:3031
17930991460,87cyclictest0-21swapper/920:50:3031
178989914628,78cyclictest0-21swapper/121:17:511
180449914525,71cyclictest0-21swapper/2921:30:2222
179579914519,98cyclictest0-21swapper/1622:58:078
180449914416,103cyclictest0-21swapper/2919:46:1122
179579914420,91cyclictest0-21swapper/1623:29:368
179309914450,57cyclictest0-21swapper/900:39:1331
17898991440,86cyclictest0-21swapper/120:50:061
17898991440,86cyclictest0-21swapper/120:50:061
17898991430,84cyclictest0-21swapper/120:03:031
179579914218,98cyclictest0-21swapper/1623:30:438
179579914119,91cyclictest0-21swapper/1622:43:438
179309914150,59cyclictest0-21swapper/900:26:5531
17930991410,85cyclictest0-21swapper/923:43:0731
17898991410,84cyclictest0-21swapper/100:30:321
17898991410,83cyclictest0-21swapper/122:05:421
17898991410,83cyclictest0-21swapper/121:10:401
17898991410,83cyclictest0-21swapper/121:10:401
17898991410,83cyclictest0-21swapper/100:25:111
17898991410,81cyclictest0-21swapper/123:33:531
178989914021,111cyclictest17169-21/usr/sbin/munin22:20:281
17898991400,83cyclictest0-21swapper/123:57:241
17898991400,82cyclictest0-21swapper/122:30:171
17898991400,79cyclictest0-21swapper/120:23:391
17898991400,79cyclictest0-21swapper/120:23:391
180449913925,79cyclictest0-21swapper/2922:30:3222
179309913952,56cyclictest0-21swapper/923:59:0831
179309913941,71cyclictest0-21swapper/921:50:5231
17898991390,88cyclictest0-21swapper/123:29:041
17898991390,82cyclictest0-21swapper/123:36:011
17898991390,82cyclictest0-21swapper/100:10:131
179309913858,57cyclictest0-21swapper/922:13:1931
179309913849,60cyclictest0-21swapper/919:52:1931
179309913828,71cyclictest0-21swapper/921:26:4931
179309913828,71cyclictest0-21swapper/921:26:4931
17898991380,84cyclictest0-21swapper/122:48:271
17898991380,82cyclictest0-21swapper/121:36:191
180449913752,62cyclictest0-21swapper/2923:19:2322
180449913715,101cyclictest0-21swapper/2923:25:1622
179409913712,83cyclictest0-21swapper/1221:42:114
179309913751,56cyclictest0-21swapper/922:33:0631
179309913747,58cyclictest0-21swapper/922:49:4031
179309913746,60cyclictest0-21swapper/900:11:5731
17930991370,80cyclictest0-21swapper/923:21:4331
17930991370,76cyclictest0-21swapper/921:05:2731
17930991370,76cyclictest0-21swapper/921:05:2731
178989913749,56cyclictest0-21swapper/121:53:251
178989913726,70cyclictest0-21swapper/121:32:341
17898991370,81cyclictest0-21swapper/122:50:241
17898991370,81cyclictest0-21swapper/121:41:391
17898991370,81cyclictest0-21swapper/119:20:371
17898991370,79cyclictest0-21swapper/119:55:201
180449913647,57cyclictest0-21swapper/2921:44:4322
18044991360,78cyclictest0-21swapper/2921:45:2022
17957991360,84cyclictest0-21swapper/1623:10:248
179309913632,73cyclictest0-21swapper/920:25:2431
179309913632,73cyclictest0-21swapper/920:25:2331
179309913629,74cyclictest0-21swapper/923:17:2731
179309913628,66cyclictest0-21swapper/921:10:4931
179309913628,66cyclictest0-21swapper/921:10:4831
17930991360,83cyclictest0-21swapper/900:16:1431
17898991360,81cyclictest0-21swapper/122:18:321
17898991360,80cyclictest0-21swapper/123:01:181
180449913543,61cyclictest0-21swapper/2900:09:3722
180269913530,103cyclictest0-21swapper/2600:10:3919
179309913531,74cyclictest0-21swapper/920:20:0231
179309913531,74cyclictest0-21swapper/920:20:0231
179309913530,67cyclictest0-21swapper/922:01:3431
179309913529,70cyclictest0-21swapper/922:52:2131
179309913529,67cyclictest0-21swapper/921:42:5131
179309913528,69cyclictest0-21swapper/900:00:4431
178989913558,62cyclictest0-21swapper/121:24:341
178989913558,62cyclictest0-21swapper/121:24:331
17898991350,84cyclictest0-21swapper/123:41:541
180449913415,99cyclictest0-21swapper/2923:24:1222
180269913428,101cyclictest0-21swapper/2621:48:2919
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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