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2023-03-29 - 01:55

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100, highest latencies:
System rackcslot8.osadl.org (updated Tue Mar 28, 2023 12:49:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25869928385,1cyclictest151rcu_preempt10:46:5529
26379918427,127cyclictest0-21swapper/1807:55:3410
2279911750,167ptp4l0-21swapper/107:07:321
26209917261,63cyclictest151rcu_preempt10:07:457
26089917217,97cyclictest151rcu_preempt11:16:204
26919916823,144cyclictest0-21swapper/2510:24:1418
26919916823,108cyclictest0-21swapper/2511:13:5818
26209915527,85cyclictest0-21swapper/1507:33:397
26089915328,80cyclictest151rcu_preempt10:00:204
26249915132,118cyclictest0-21swapper/1611:05:358
2642991508,76cyclictest0-21swapper/1908:30:1911
2642991508,76cyclictest0-21swapper/1908:30:1911
26249914830,70cyclictest0-21swapper/1609:20:188
26249914627,96cyclictest0-21swapper/1611:10:278
26249914627,90cyclictest0-21swapper/1609:15:318
26249914627,90cyclictest0-21swapper/1609:15:308
2608991468,121cyclictest151rcu_preempt09:58:174
2691991450,87cyclictest0-21swapper/2512:32:3018
2642991458,82cyclictest0-21swapper/1910:25:1311
2691991440,87cyclictest0-21swapper/2509:35:0418
2691991440,85cyclictest0-21swapper/2507:56:4618
26249914324,83cyclictest0-21swapper/1611:32:548
2642991420,106cyclictest0-21swapper/1909:46:1211
2691991410,83cyclictest0-21swapper/2508:35:1418
2691991410,83cyclictest0-21swapper/2508:35:1418
2691991410,81cyclictest0-21swapper/2508:05:1818
26249914127,70cyclictest0-21swapper/1611:49:458
26209914121,87cyclictest0-21swapper/1511:30:217
2620991410,80cyclictest0-21swapper/1509:00:107
2620991410,80cyclictest0-21swapper/1509:00:107
26999914014,118cyclictest0-21swapper/2612:05:1719
26249914032,60cyclictest0-21swapper/1610:40:008
2620991400,79cyclictest0-21swapper/1509:06:367
2620991400,79cyclictest0-21swapper/1509:06:357
26579913918,66cyclictest0-21swapper/2110:55:2914
2642991398,95cyclictest0-21swapper/1911:15:2611
26919913830,66cyclictest0-21swapper/2512:27:3418
2691991380,85cyclictest0-21swapper/2507:55:0018
26429913820,67cyclictest0-21swapper/1910:14:3111
2637991380,81cyclictest0-21swapper/1807:44:3710
27299913719,48cyclictest151rcu_preempt11:16:4324
2699991370,87cyclictest0-21swapper/2609:42:0219
2691991370,83cyclictest0-21swapper/2510:47:1318
26919913624,71cyclictest0-21swapper/2511:45:1718
26379913625,73cyclictest0-21swapper/1812:35:0410
26209913624,81cyclictest0-21swapper/1511:26:527
26919913533,62cyclictest0-21swapper/2511:50:1718
26919913529,65cyclictest0-21swapper/2508:40:3418
26919913529,65cyclictest0-21swapper/2508:40:3418
2691991350,83cyclictest0-21swapper/2510:57:2418
2691991350,82cyclictest0-21swapper/2511:25:1018
26919913445,55cyclictest0-21swapper/2512:20:1318
26919913430,64cyclictest0-21swapper/2509:00:2018
26919913430,64cyclictest0-21swapper/2509:00:2018
26919913428,65cyclictest0-21swapper/2510:35:2918
2608991340,86cyclictest0-21swapper/1209:38:574
26919913344,64cyclictest0-21swapper/2509:40:2518
26919913331,64cyclictest0-21swapper/2509:47:2218
26919913330,66cyclictest0-21swapper/2511:00:0318
26919913329,63cyclictest0-21swapper/2510:06:0518
2691991330,82cyclictest0-21swapper/2509:54:5118
2642991338,87cyclictest0-21swapper/1910:36:5811
26379913325,63cyclictest0-21swapper/1810:41:1410
26919913231,69cyclictest0-21swapper/2510:15:0918
26919913230,65cyclictest0-21swapper/2508:17:3618
26919913230,65cyclictest0-21swapper/2508:17:3618
26919913230,64cyclictest0-21swapper/2507:35:2318
26919913129,71cyclictest0-21swapper/2509:16:2318
26919913129,71cyclictest0-21swapper/2509:16:2218
26919913129,66cyclictest0-21swapper/2512:17:3218
26379913146,59cyclictest0-21swapper/1811:58:1110
26379913140,58cyclictest0-21swapper/1809:30:4110
26379913127,71cyclictest0-21swapper/1807:25:2610
26379913127,68cyclictest0-21swapper/1811:44:4910
26089913112,98cyclictest147052cat09:45:264
26919913031,66cyclictest0-21swapper/2510:02:5318
26919913029,64cyclictest0-21swapper/2510:42:2518
26919913029,59cyclictest0-21swapper/2507:15:3818
26919913027,62cyclictest0-21swapper/2512:10:3518
26379913029,67cyclictest0-21swapper/1811:11:4010
26379913028,74cyclictest0-21swapper/1809:18:2210
26379913028,74cyclictest0-21swapper/1809:18:2110
26379913028,68cyclictest0-21swapper/1809:47:1510
26379913028,67cyclictest0-21swapper/1811:34:4010
26379913028,67cyclictest0-21swapper/1809:44:3510
26379913027,70cyclictest0-21swapper/1808:30:1810
26379913027,70cyclictest0-21swapper/1808:30:1810
26379913027,67cyclictest0-21swapper/1809:58:5910
26379913026,67cyclictest0-21swapper/1809:21:3710
26209913051,73cyclictest0-21swapper/1507:38:287
26919912931,70cyclictest0-21swapper/2511:23:3418
26919912930,69cyclictest0-21swapper/2511:43:5318
26919912929,64cyclictest0-21swapper/2509:14:4618
26919912929,62cyclictest0-21swapper/2507:10:1818
2691991290,76cyclictest0-21swapper/2509:55:2418
2691991290,75cyclictest0-21swapper/2510:10:2118
2642991298,80cyclictest0-21swapper/1911:42:1011
26429912925,65cyclictest0-21swapper/1910:32:4311
26379912932,76cyclictest0-21swapper/1809:11:2710
26379912928,72cyclictest0-21swapper/1810:36:5510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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