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2025-03-24 - 01:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Sun Mar 23, 2025 12:50:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
903899317118,1cyclictest151rcu_preempt10:55:264
91579928284,1cyclictest151rcu_preempt11:56:3821
89909921519,38cyclictest151rcu_preempt11:06:4327
2482911770,168ptp4l0-21swapper/107:05:251
9103991761,173cyclictest0-21swapper/2112:26:5714
90689917537,129cyclictest0-21swapper/1612:39:518
90389917492,82cyclictest88-21ksoftirqd/1211:56:044
912599170164,5cyclictest151rcu_preempt10:30:1118
90689917031,101cyclictest0-21swapper/1611:08:198
90689916727,124cyclictest0-21swapper/1612:17:258
91039916536,125cyclictest0-21swapper/2109:35:0414
90689916530,117cyclictest0-21swapper/1608:55:158
90689916530,117cyclictest0-21swapper/1608:55:158
909599164162,1cyclictest151rcu_preempt09:33:3113
91259916320,100cyclictest0-21swapper/2508:40:2518
91259916320,100cyclictest0-21swapper/2508:40:2518
91039916335,110cyclictest0-21swapper/2109:30:1514
90689916331,124cyclictest0-21swapper/1608:20:118
90689916331,124cyclictest0-21swapper/1608:20:118
91259916066,6cyclictest0-21swapper/2510:24:5018
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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