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2024-04-23 - 23:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Tue Apr 23, 2024 12:48:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159439916349,35cyclictest0-21swapper/2411:55:1617
159689915025,84cyclictest0-21swapper/3011:22:4424
159439914831,68cyclictest0-21swapper/2410:30:0017
159529914611,131cyclictest151rcu_preempt11:56:2019
159439914610,100cyclictest151rcu_preempt08:27:4517
159169914530,70cyclictest0-21swapper/1810:01:4810
159169914530,70cyclictest0-21swapper/1810:01:4810
158409914554,89cyclictest0-21swapper/308:30:1223
159649914426,117cyclictest0-21swapper/2912:35:2422
159649914326,116cyclictest0-21swapper/2910:30:2022
159649914326,116cyclictest0-21swapper/2910:25:3222
159649914326,116cyclictest0-21swapper/2909:11:1422
159259914316,84cyclictest0-21swapper/2012:30:2813
15840991420,83cyclictest0-21swapper/311:17:0923
159259914116,70cyclictest0-21swapper/2012:00:1913
159259914116,101cyclictest0-21swapper/2010:56:5013
159259914016,71cyclictest0-21swapper/2009:10:2113
15916991390,85cyclictest0-21swapper/1811:43:2210
15907991390,89cyclictest0-21swapper/1709:10:309
158869913936,102cyclictest0-21swapper/1212:25:174
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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