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2026-01-25 - 13:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Sun Jan 25, 2026 00:48:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912880,280ptp4l0-21swapper/119:09:391
15229927780,2cyclictest151rcu_preempt00:01:510
15959923478,1cyclictest931rcuc/1323:22:275
15429921721,126cyclictest0-21swapper/422:55:2326
15429921121,124cyclictest0-21swapper/422:40:2326
16619917757,72cyclictest0-21swapper/2200:17:0615
16619915549,61cyclictest0-21swapper/2223:29:0015
16619915431,86cyclictest0-21swapper/2222:46:1415
15259914820,108cyclictest0-21swapper/123:19:331
16619914756,60cyclictest0-21swapper/2223:03:4615
15259914727,76cyclictest0-21swapper/123:50:011
15429914621,124cyclictest0-21swapper/421:22:5326
15429914621,124cyclictest0-21swapper/421:22:5326
16619914548,57cyclictest0-21swapper/2221:00:2515
16619914548,57cyclictest0-21swapper/2221:00:2515
15429914521,33cyclictest0-21swapper/420:12:3526
15429914521,33cyclictest0-21swapper/420:12:3526
15429914521,122cyclictest0-21swapper/400:18:4126
1525991450,86cyclictest0-21swapper/119:53:481
15229914532,37cyclictest0-21swapper/000:00:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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