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2024-07-27 - 08:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Sat Jul 27, 2024 00:49:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22660992058,1cyclictest151rcu_preempt00:06:3110
22660992058,1cyclictest151rcu_preempt00:06:3110
2279912010,185ptp4l0-21swapper/119:05:181
225229919128,141cyclictest0-21swapper/221:10:5012
225499918912,89cyclictest0-21swapper/521:40:1727
226999918510,126cyclictest0-21swapper/2321:34:2416
225229917826,151cyclictest0-21swapper/219:10:2112
225229917826,151cyclictest0-21swapper/219:10:2112
225229917525,109cyclictest0-21swapper/222:52:0412
225229916520,106cyclictest0-21swapper/223:05:1412
225229916226,91cyclictest0-21swapper/220:30:1312
225499915812,90cyclictest0-21swapper/523:06:1927
227569915552,21cyclictest0-21swapper/3019:30:1924
227569915552,21cyclictest0-21swapper/3019:30:1924
22699991555,106cyclictest0-21swapper/2323:20:3116
22699991555,106cyclictest0-21swapper/2323:20:3116
22522991550,114cyclictest0-21swapper/200:39:1512
22522991550,114cyclictest0-21swapper/200:39:1512
226999915410,102cyclictest0-21swapper/2323:38:4116
22540991490,98cyclictest18287-21hddtemp_smartct00:10:1726
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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