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2025-07-04 - 09:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Fri Jul 04, 2025 00:49:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482913180,310ptp4l0-21swapper/119:05:541
284959921214,2cyclictest151rcu_preempt23:20:131
284959921214,2cyclictest151rcu_preempt23:20:121
286169916631,102cyclictest0-21swapper/1719:35:149
285309916529,126cyclictest0-21swapper/600:02:1528
285309916529,126cyclictest0-21swapper/600:02:1528
28703991637,154cyclictest151rcu_preempt23:35:4921
28703991637,154cyclictest151rcu_preempt23:35:4821
28530991589,141cyclictest52-21ksoftirqd/623:14:0928
2482911570,54ptp4l22-21ksoftirqd/122:21:141
287039914919,127cyclictest151rcu_preempt00:08:1921
287039914919,127cyclictest151rcu_preempt00:08:1921
287039914910,101cyclictest0-21swapper/2823:42:5521
287039914910,101cyclictest0-21swapper/2823:42:5521
286169914846,62cyclictest0-21swapper/1719:55:219
287039914519,106cyclictest0-21swapper/2822:30:1421
285819914437,77cyclictest0-21swapper/1300:09:515
285819914437,77cyclictest0-21swapper/1300:09:515
287039914110,128cyclictest151rcu_preempt00:28:0621
287039914110,128cyclictest151rcu_preempt00:28:0521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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