You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2021-01-27 - 11:10

AMD Ryzen Threadripper 1950X 16-Core Processor, Linux 5.4.59-rt36 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Wed Jan 27, 2021 01:52:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2872912940,284ptp4l0-21swapper/119:09:191
508129919021,84cyclictest0-21swapper/2400:00:0917
508129919021,84cyclictest0-21swapper/2400:00:0917
508219918090,81cyclictest0-21swapper/2500:39:1918
50654991747,115cyclictest0-21swapper/622:08:2056
50864991710,118cyclictest0-21swapper/3021:58:3524
50654991696,134cyclictest0-21swapper/621:16:1156
50654991696,100cyclictest0-21swapper/623:53:0656
50654991696,100cyclictest0-21swapper/623:53:0556
50864991670,132cyclictest0-21swapper/3000:00:5024
50864991670,132cyclictest0-21swapper/3000:00:4924
50864991650,119cyclictest0-21swapper/3023:25:1024
50654991636,93cyclictest0-21swapper/620:40:0856
50864991601,135cyclictest0-21swapper/3022:56:5124
50864991601,135cyclictest0-21swapper/3022:56:5124
5077699160120,1cyclictest121rcu_preempt23:51:1813
5077699160120,1cyclictest121rcu_preempt23:51:1813
506459915175,75cyclictest0-21swapper/520:50:0845
506459915120,27cyclictest0-21swapper/520:43:3245
50864991490,109cyclictest0-21swapper/3022:08:1324
5229021470,6sleep155073099cyclictest21:35:067
50864991470,146cyclictest0-21swapper/3022:24:4624
506459914751,58cyclictest0-21swapper/520:15:0045
50679991460,75cyclictest0-21swapper/923:30:1063
50679991460,75cyclictest0-21swapper/923:30:1063
50654991436,91cyclictest0-21swapper/621:01:1156
50654991416,109cyclictest0-21swapper/600:16:3656
506459914134,15cyclictest0-21swapper/500:33:3145
50864991403,101cyclictest0-21swapper/3022:32:1524
508709913940,41cyclictest0-21swapper/3100:36:1625
508219913984,33cyclictest190-21ksoftirqd/2500:23:1218
5081299137133,1cyclictest121rcu_preempt21:55:0617
50654991366,87cyclictest0-21swapper/622:00:1956
506459913622,18cyclictest0-21swapper/500:03:3845
506459913622,18cyclictest0-21swapper/500:03:3845
506459913550,49cyclictest0-21swapper/520:15:0145
508129913423,110cyclictest0-21swapper/2423:45:1617
508129913423,110cyclictest0-21swapper/2423:45:1617
5081299133133,0cyclictest121rcu_preempt22:54:5917
50654991336,94cyclictest0-21swapper/600:26:4656
506459913374,41cyclictest0-21swapper/520:45:0445
50654991326,88cyclictest0-21swapper/619:40:3356
506459913225,58cyclictest0-21swapper/523:18:1045
506459913225,58cyclictest0-21swapper/523:18:0945
508129913123,107cyclictest0-21swapper/2423:35:1917
508129913123,107cyclictest0-21swapper/2423:35:1917
506459913150,54cyclictest0-21swapper/520:40:0145
506459913148,53cyclictest0-21swapper/522:17:1145
508129913023,93cyclictest0-21swapper/2422:11:3917
508129913023,89cyclictest0-21swapper/2423:10:0217
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional