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2023-01-29 - 16:46

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Sun Jan 29, 2023 12:50:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318319928890,1cyclictest151rcu_preempt10:11:024
318319928890,1cyclictest151rcu_preempt09:48:324
318319928890,1cyclictest151rcu_preempt09:48:324
318319928689,2cyclictest151rcu_preempt11:01:104
318319928689,2cyclictest151rcu_preempt11:01:104
3179999188187,0cyclictest64-21ksoftirqd/812:38:2730
317429916810,143cyclictest22-21ksoftirqd/112:34:301
31936991410,86cyclictest0-21swapper/2609:53:4719
31936991410,84cyclictest0-21swapper/2611:35:2019
31936991410,84cyclictest0-21swapper/2611:35:2019
317999914143,72cyclictest0-21swapper/810:43:5630
317999914143,72cyclictest0-21swapper/810:43:5630
31890991404,104cyclictest151rcu_preempt11:15:1613
31890991404,104cyclictest151rcu_preempt11:15:1513
31799991380,80cyclictest0-21swapper/810:10:2330
317429913838,77cyclictest0-21swapper/111:31:421
317429913838,77cyclictest0-21swapper/111:31:421
31742991380,86cyclictest0-21swapper/110:11:311
317999913647,58cyclictest0-21swapper/811:32:1730
317999913647,58cyclictest0-21swapper/811:32:1730
31742991360,84cyclictest0-21swapper/110:39:521
319619913463,44cyclictest0-21swapper/2909:14:1722
317999913428,70cyclictest0-21swapper/807:51:4730
317999913426,70cyclictest0-21swapper/807:38:3730
31799991340,81cyclictest0-21swapper/808:05:2230
317429913433,99cyclictest0-21swapper/111:25:501
317429913433,99cyclictest0-21swapper/111:25:501
317429913432,73cyclictest0-21swapper/110:30:021
317429913432,73cyclictest0-21swapper/110:30:021
31961991330,77cyclictest0-21swapper/2910:10:1122
317999913329,65cyclictest0-21swapper/811:35:2230
317999913329,65cyclictest0-21swapper/811:35:2230
317999913328,70cyclictest0-21swapper/808:20:1530
317999913327,65cyclictest0-21swapper/810:32:3230
317999913327,65cyclictest0-21swapper/810:32:3230
317429913332,74cyclictest0-21swapper/109:50:161
317999913231,67cyclictest0-21swapper/809:15:2730
317999913229,68cyclictest0-21swapper/811:47:5330
317999913229,68cyclictest0-21swapper/811:47:5330
317999913229,67cyclictest0-21swapper/808:59:0630
317999913226,85cyclictest0-21swapper/809:55:2730
319619913134,31cyclictest0-21swapper/2911:41:3722
319619913134,31cyclictest0-21swapper/2911:41:3722
317999913131,69cyclictest0-21swapper/809:10:0130
317999913126,71cyclictest0-21swapper/811:07:0330
317999913126,71cyclictest0-21swapper/811:07:0330
317429913131,88cyclictest0-21swapper/111:42:561
317429913131,88cyclictest0-21swapper/111:42:561
317999913045,57cyclictest0-21swapper/808:00:0030
317999913042,52cyclictest0-21swapper/810:15:1230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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