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2022-01-22 - 15:36

AMD Ryzen Threadripper 1950X 16-Core Processor, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Sat Jan 22, 2022 12:50:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2316299344146,1cyclictest151rcu_preempt11:02:319
2314399319121,2cyclictest151rcu_preempt11:22:135
2096912170,209ptp4l0-21swapper/107:08:131
231439918627,78cyclictest0-21swapper/1309:50:015
231209917316,156cyclictest0-21swapper/810:26:3430
2315299170164,5cyclictest0-21swapper/1510:19:247
231209916215,121cyclictest0-21swapper/807:50:0230
231039915815,106cyclictest0-21swapper/409:32:3226
231529915619,86cyclictest0-21swapper/1510:29:497
2319999155128,1cyclictest151rcu_preempt12:32:0716
231529915019,76cyclictest0-21swapper/1509:38:507
231209914816,82cyclictest0-21swapper/809:17:2330
231209914816,82cyclictest0-21swapper/809:17:2230
23193991430,88cyclictest0-21swapper/2210:54:1115
231529914319,91cyclictest0-21swapper/1509:57:317
23212991410,83cyclictest0-21swapper/2507:40:2318
23108991410,90cyclictest0-21swapper/511:22:5327
231529913916,94cyclictest0-21swapper/1508:05:517
231529913916,94cyclictest0-21swapper/1508:05:517
23152991390,81cyclictest0-21swapper/1509:20:087
231349913728,65cyclictest0-21swapper/1109:45:113
23084991370,86cyclictest0-21swapper/009:00:010
23084991370,86cyclictest0-21swapper/009:00:000
23120991360,83cyclictest0-21swapper/809:45:2930
231209913516,86cyclictest0-21swapper/810:20:1230
232429913431,94cyclictest0-21swapper/3009:46:3324
230849913450,57cyclictest0-21swapper/011:13:400
230849913442,60cyclictest0-21swapper/009:49:330
232429913332,53cyclictest0-21swapper/3010:47:2924
23108991330,84cyclictest0-21swapper/509:58:5827
230939913363,47cyclictest23078-21cyclictest11:55:5612
230849913321,33cyclictest0-21swapper/010:51:490
232429913231,80cyclictest0-21swapper/3010:15:2424
231349913225,61cyclictest0-21swapper/1110:33:323
231209913216,116cyclictest0-21swapper/808:10:2030
231209913216,116cyclictest0-21swapper/808:10:2030
232429913130,55cyclictest0-21swapper/3010:20:4824
232429913128,74cyclictest0-21swapper/3009:17:0924
232429913128,74cyclictest0-21swapper/3009:17:0924
23212991310,79cyclictest0-21swapper/2510:43:3118
231529913119,111cyclictest0-21swapper/1510:40:177
231349913128,64cyclictest0-21swapper/1109:40:213
230849913136,62cyclictest0-21swapper/010:40:540
230849913127,61cyclictest0-21swapper/009:15:230
230849913127,61cyclictest0-21swapper/009:15:230
230849913125,62cyclictest0-21swapper/010:45:430
23212991300,74cyclictest0-21swapper/2512:19:5118
231399913070,45cyclictest0-21swapper/1207:11:364
231399913024,66cyclictest0-21swapper/1209:45:104
231349913028,61cyclictest0-21swapper/1109:39:493
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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