You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-06-11 - 02:42

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Sat Jun 10, 2023 12:47:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231191271263,6phc2sys0-21swapper/207:05:2712
231191271263,6phc2sys0-21swapper/207:05:2612
2279912340,226ptp4l0-21swapper/107:09:151
2279912340,226ptp4l0-21swapper/107:09:151
67969920616,154cyclictest24633-21fschecks_time11:40:2629
6903991450,81cyclictest0-21swapper/2408:52:1217
55472144137,6sleep260-21swapper/2607:09:3619
55472144137,6sleep260-21swapper/2607:09:3619
68529914053,66cyclictest0-21swapper/1609:01:398
6852991400,80cyclictest0-21swapper/1612:27:358
6852991400,80cyclictest0-21swapper/1612:27:358
68529913948,61cyclictest0-21swapper/1612:15:228
68529913948,61cyclictest0-21swapper/1612:15:228
68529913945,60cyclictest0-21swapper/1611:33:388
68529913929,92cyclictest0-21swapper/1608:21:508
68219913949,61cyclictest0-21swapper/1109:10:213
68219913945,57cyclictest0-21swapper/1110:20:213
6903991380,81cyclictest0-21swapper/2411:40:0117
68529913830,71cyclictest0-21swapper/1609:45:318
68529913828,66cyclictest0-21swapper/1612:06:148
68529913828,66cyclictest0-21swapper/1612:06:138
6852991380,34cyclictest0-21swapper/1610:25:348
68529913730,75cyclictest0-21swapper/1610:55:448
68529913627,75cyclictest0-21swapper/1611:50:008
68529913627,75cyclictest0-21swapper/1611:50:008
68219913629,65cyclictest0-21swapper/1111:23:553
68529913539,70cyclictest0-21swapper/1612:00:258
68529913539,70cyclictest0-21swapper/1612:00:258
68529913531,77cyclictest0-21swapper/1608:34:068
68529913529,65cyclictest0-21swapper/1608:45:048
68529913526,66cyclictest0-21swapper/1609:35:228
68219913529,63cyclictest0-21swapper/1109:48:493
68529913429,70cyclictest0-21swapper/1612:23:198
68529913429,70cyclictest0-21swapper/1612:23:198
68529913429,67cyclictest0-21swapper/1608:40:248
68219913431,69cyclictest0-21swapper/1110:15:463
68219913428,61cyclictest0-21swapper/1109:52:393
68529913330,68cyclictest0-21swapper/1607:59:398
68529913329,74cyclictest0-21swapper/1611:10:278
68529913329,70cyclictest0-21swapper/1610:15:258
68529913327,68cyclictest0-21swapper/1609:25:278
68529913325,68cyclictest0-21swapper/1608:50:578
68529913316,71cyclictest0-21swapper/1610:05:228
68219913348,68cyclictest0-21swapper/1111:39:573
68219913329,62cyclictest0-21swapper/1111:10:013
68219913328,59cyclictest0-21swapper/1109:32:213
67499913334,58cyclictest0-21swapper/208:30:5412
68529913235,70cyclictest0-21swapper/1610:40:018
68529913228,72cyclictest0-21swapper/1607:15:248
6907991311,90cyclictest0-21swapper/2511:46:0418
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional