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2024-07-21 - 21:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Sun Jul 21, 2024 12:48:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231191203195,6phc2sys0-21swapper/207:05:1012
180479917827,150cyclictest0-21swapper/1907:16:0011
180479917827,150cyclictest0-21swapper/1907:16:0011
180879917229,107cyclictest0-21swapper/2312:08:1516
1801499171170,0cyclictest106-21ksoftirqd/1512:18:247
180879917028,99cyclictest0-21swapper/2309:59:2816
2279911660,157ptp4l0-21swapper/107:06:411
180959916365,76cyclictest0-21swapper/2411:12:5117
180479915827,87cyclictest0-21swapper/1910:27:5011
180479915719,104cyclictest0-21swapper/1910:50:1811
17922991528,134cyclictest0-21swapper/411:30:3226
18087991510,87cyclictest0-21swapper/2309:36:2916
1799799151114,32cyclictest0-21swapper/1308:41:105
18087991491,89cyclictest0-21swapper/2311:47:3316
18047991490,90cyclictest0-21swapper/1912:05:0711
179009914832,106cyclictest0-21swapper/109:49:351
18095991460,84cyclictest0-21swapper/2409:56:2617
179009914627,83cyclictest0-21swapper/109:15:231
18087991450,86cyclictest0-21swapper/2310:11:2016
18047991450,89cyclictest0-21swapper/1911:34:0611
179669914534,100cyclictest0-21swapper/911:48:5531
179229914533,78cyclictest0-21swapper/408:55:0026
179009914532,58cyclictest0-21swapper/108:05:231
179009914532,58cyclictest0-21swapper/108:05:231
18087991440,86cyclictest0-21swapper/2311:00:3116
179229914434,83cyclictest0-21swapper/407:10:1526
179009914426,96cyclictest0-21swapper/107:10:221
18095991430,84cyclictest0-21swapper/2411:05:0817
179669914333,86cyclictest0-21swapper/910:18:3531
179009914329,71cyclictest0-21swapper/108:10:591
179009914329,71cyclictest0-21swapper/108:10:591
18087991420,84cyclictest0-21swapper/2308:15:2416
18087991420,84cyclictest0-21swapper/2308:15:2316
179669914237,54cyclictest0-21swapper/910:26:1231
18087991410,84cyclictest0-21swapper/2309:16:3116
18087991410,81cyclictest0-21swapper/2311:20:1516
17922991410,85cyclictest0-21swapper/409:28:0426
18087991400,83cyclictest0-21swapper/2308:26:0516
18087991400,83cyclictest0-21swapper/2308:26:0416
18087991400,82cyclictest0-21swapper/2308:00:2616
18087991400,82cyclictest0-21swapper/2308:00:2516
18087991400,79cyclictest0-21swapper/2307:15:3216
18087991400,79cyclictest0-21swapper/2307:15:3116
179669914037,62cyclictest0-21swapper/911:22:3931
179669914033,73cyclictest0-21swapper/911:35:0031
18087991390,83cyclictest0-21swapper/2309:10:0616
179669913930,84cyclictest0-21swapper/909:15:3131
179669913928,91cyclictest0-21swapper/909:43:1931
180879913826,70cyclictest0-21swapper/2312:00:4616
180879913748,57cyclictest0-21swapper/2309:25:2216
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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