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2022-07-05 - 02:25

x86 AMD 1950X @3700 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #c, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Mon Jul 04, 2022 12:49:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1850899311114,1cyclictest151rcu_preempt11:49:1830
157582225217,6sleep160-21swapper/1607:05:238
1866799182164,3cyclictest151rcu_preempt09:13:3621
186679917730,87cyclictest0-21swapper/2808:45:0121
18524991779,118cyclictest0-21swapper/1011:35:232
18524991779,118cyclictest0-21swapper/1011:35:232
268191175167,6phc2sys0-21swapper/207:05:2312
2642911560,148ptp4l0-21swapper/107:06:461
18577991450,88cyclictest0-21swapper/1711:24:179
18524991450,52cyclictest0-21swapper/1007:35:192
18577991440,89cyclictest0-21swapper/1712:30:209
18479991440,84cyclictest0-21swapper/410:15:2726
186679914059,80cyclictest0-21swapper/2812:22:4521
185249914049,57cyclictest0-21swapper/1012:02:382
185699913915,74cyclictest0-21swapper/1609:45:298
18524991399,82cyclictest0-21swapper/1011:30:002
18524991399,82cyclictest0-21swapper/1011:30:002
185699913820,88cyclictest0-21swapper/1611:32:198
185699913820,88cyclictest0-21swapper/1611:32:198
185249913859,70cyclictest0-21swapper/1012:07:592
185249913845,60cyclictest0-21swapper/1009:13:142
185249913655,70cyclictest0-21swapper/1009:00:242
185249913647,55cyclictest0-21swapper/1012:38:592
185249913646,54cyclictest0-21swapper/1012:18:402
185249913529,64cyclictest0-21swapper/1007:40:162
185249913529,62cyclictest0-21swapper/1008:00:022
18577991340,79cyclictest0-21swapper/1712:35:209
185249913436,63cyclictest0-21swapper/1009:15:222
185249913429,66cyclictest0-21swapper/1011:32:112
185249913429,66cyclictest0-21swapper/1011:32:112
185249913428,66cyclictest0-21swapper/1012:26:412
185249913428,62cyclictest0-21swapper/1011:10:162
185249913428,62cyclictest0-21swapper/1011:10:162
185779913365,68cyclictest0-21swapper/1711:44:219
185779913365,68cyclictest0-21swapper/1711:44:219
185699913326,62cyclictest0-21swapper/1611:13:538
185699913326,62cyclictest0-21swapper/1611:13:538
185249913335,65cyclictest0-21swapper/1010:39:482
185249913335,65cyclictest0-21swapper/1010:39:482
18524991330,78cyclictest0-21swapper/1009:20:492
18479991330,81cyclictest0-21swapper/408:35:3326
185779913220,85cyclictest0-21swapper/1712:12:589
185539913244,51cyclictest0-21swapper/1411:56:506
185249913235,65cyclictest0-21swapper/1008:10:112
185249913230,64cyclictest0-21swapper/1009:38:212
185249913229,67cyclictest0-21swapper/1010:30:432
185249913229,67cyclictest0-21swapper/1010:30:432
185249913228,60cyclictest0-21swapper/1009:52:462
18479991320,81cyclictest0-21swapper/409:07:2726
18479991320,81cyclictest0-21swapper/409:07:2726
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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