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2025-07-14 - 22:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Mon Jul 14, 2025 12:49:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482913680,359ptp4l0-21swapper/107:05:151
250989921718,2cyclictest151rcu_preempt11:45:2013
329891188177,9phc2sys0-21swapper/207:05:1612
249679917681,0cyclictest151rcu_preempt11:01:300
249889917021,95cyclictest0-21swapper/410:44:2626
249889916221,97cyclictest0-21swapper/411:21:4326
249779916119,114cyclictest0-21swapper/210:40:2012
249779916019,106cyclictest0-21swapper/207:25:1812
249779915819,85cyclictest0-21swapper/209:30:1812
249779915719,85cyclictest0-21swapper/209:35:0812
249779915719,85cyclictest0-21swapper/209:35:0812
249839915522,97cyclictest0-21swapper/311:24:0923
249839915522,125cyclictest0-21swapper/309:27:4023
249839915522,125cyclictest0-21swapper/309:27:3923
249839915522,104cyclictest0-21swapper/311:40:1223
249839915222,72cyclictest0-21swapper/309:53:1823
249839915222,72cyclictest0-21swapper/309:53:1823
250629915122,81cyclictest106-21ksoftirqd/1509:39:107
250629915122,81cyclictest106-21ksoftirqd/1509:39:097
249839915022,82cyclictest0-21swapper/310:34:5923
24983991500,86cyclictest0-21swapper/310:10:2523
24983991500,86cyclictest0-21swapper/310:10:2423
249839914822,125cyclictest0-21swapper/312:20:1623
249839914622,123cyclictest0-21swapper/311:50:2223
249779914625,120cyclictest151rcu_preempt09:20:4212
249779914625,120cyclictest151rcu_preempt09:20:4112
25161991450,86cyclictest0-21swapper/2912:30:1922
250789914533,111cyclictest0-21swapper/1710:25:059
250789914432,102cyclictest0-21swapper/1710:20:499
250789914432,102cyclictest0-21swapper/1710:20:499
250199914457,59cyclictest0-21swapper/909:21:5231
250199914457,59cyclictest0-21swapper/909:21:5231
249779914419,86cyclictest0-21swapper/209:29:4512
249779914419,86cyclictest0-21swapper/209:29:4512
249679914123,91cyclictest0-21swapper/011:28:270
251619914051,56cyclictest0-21swapper/2909:38:1522
251619914051,56cyclictest0-21swapper/2909:38:1422
251559914035,56cyclictest0-21swapper/2811:15:1921
25105991400,86cyclictest0-21swapper/2111:25:1914
251619913949,59cyclictest0-21swapper/2909:46:4822
251619913949,59cyclictest0-21swapper/2909:46:4722
251619913923,70cyclictest0-21swapper/2908:41:3622
25161991390,80cyclictest0-21swapper/2911:32:3722
251619913847,57cyclictest0-21swapper/2911:25:4122
251619913756,63cyclictest0-21swapper/2908:10:2322
251619913750,65cyclictest0-21swapper/2907:40:2922
251619913749,60cyclictest0-21swapper/2910:57:2122
251559913732,67cyclictest0-21swapper/2809:29:4321
251559913732,67cyclictest0-21swapper/2809:29:4221
251559913730,101cyclictest0-21swapper/2810:14:2121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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