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2023-12-06 - 05:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Wed Dec 06, 2023 00:49:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
141599930362,45cyclictest151rcu_preempt00:16:430
142159925233,155cyclictest0-21swapper/1300:34:155
142159918633,111cyclictest0-21swapper/1321:19:115
142159918231,100cyclictest0-21swapper/1322:12:565
142159917228,95cyclictest0-21swapper/1323:21:355
142159917228,95cyclictest0-21swapper/1323:21:345
141959915025,37cyclictest0-21swapper/823:33:5030
141959915025,37cyclictest0-21swapper/823:33:5030
141959914925,109cyclictest0-21swapper/800:20:3830
141959914826,99cyclictest0-21swapper/821:20:1330
141959914826,82cyclictest0-21swapper/821:31:1130
14178991482,86cyclictest0-21swapper/422:10:4426
141959914725,71cyclictest0-21swapper/823:21:1830
141959914725,71cyclictest0-21swapper/823:21:1830
141959914725,67cyclictest0-21swapper/822:36:5630
231191146138,6phc2sys0-21swapper/219:06:2312
141959914625,68cyclictest0-21swapper/823:15:2430
141959914423,78cyclictest0-21swapper/822:21:3330
141959914423,78cyclictest0-21swapper/822:21:3230
14215991420,85cyclictest0-21swapper/1322:18:315
14215991420,85cyclictest0-21swapper/1322:18:305
142219914179,10cyclictest151rcu_preempt23:50:066
142219914179,10cyclictest151rcu_preempt23:50:066
141959914123,79cyclictest0-21swapper/822:55:3730
141959914123,79cyclictest0-21swapper/822:55:3730
14259991390,82cyclictest0-21swapper/1920:26:2111
142159913930,78cyclictest0-21swapper/1322:25:275
142159913919,89cyclictest0-21swapper/1321:30:255
142539913844,60cyclictest0-21swapper/1822:54:5510
142539913844,60cyclictest0-21swapper/1822:54:5510
141959913825,69cyclictest0-21swapper/821:50:2530
141639913718,118cyclictest0-21swapper/123:50:311
141639913718,118cyclictest0-21swapper/123:50:301
14259991354,71cyclictest0-21swapper/1921:11:4911
141959913525,63cyclictest0-21swapper/821:10:2130
141599913540,86cyclictest0-21swapper/022:51:450
141599913540,86cyclictest0-21swapper/022:51:440
143309913431,37cyclictest151rcu_preempt20:45:3821
142539913337,61cyclictest0-21swapper/1823:25:2410
142159913329,70cyclictest0-21swapper/1323:18:225
142159913327,68cyclictest0-21swapper/1322:50:035
142159913327,68cyclictest0-21swapper/1322:50:035
142159913327,64cyclictest0-21swapper/1319:48:215
142159913325,62cyclictest0-21swapper/1300:28:555
141959913318,83cyclictest0-21swapper/823:08:2830
141959913318,83cyclictest0-21swapper/823:08:2830
14253991320,87cyclictest0-21swapper/1822:57:0510
14253991320,87cyclictest0-21swapper/1822:57:0510
142159913249,61cyclictest0-21swapper/1321:52:115
142159913229,68cyclictest0-21swapper/1322:41:305
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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