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2025-07-10 - 07:16

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Thu Jul 10, 2025 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3059021200,1sleep20-21swapper/219:10:002
108142660,1sleep110817-21cpuspeed_turbos19:35:151
114091580,2ptp4l0-21swapper/619:05:166
136122570,0sleep20-21swapper/223:55:172
2120915534,6phc2sys0-21swapper/119:05:511
3034125444,6sleep70-21swapper/719:08:157
2120915139,7phc2sys0-21swapper/519:08:115
3033725039,6sleep30-21swapper/319:08:113
3026124937,7sleep00-21swapper/019:07:110
3044924735,7sleep40-21swapper/419:09:394
114091360,1ptp4l2418-21wc20:25:205
114091330,0ptp4l0-21swapper/421:30:234
114091330,0ptp4l0-21swapper/123:55:151
114091320,0ptp4l9959-21unixbench_singl22:20:221
114091310,0ptp4l0-21swapper/621:15:396
114091310,0ptp4l0-21swapper/122:45:141
114091300,0ptp4l0-21swapper/522:45:175
114091300,0ptp4l0-21swapper/521:25:155
114091300,0ptp4l0-21swapper/420:00:184
114091300,0ptp4l0-21swapper/400:34:294
114091290,3ptp4l0-21swapper/121:52:181
114091290,0ptp4l0-21swapper/422:41:334
114091290,0ptp4l0-21swapper/222:06:302
114091290,0ptp4l0-21swapper/123:26:331
114091290,0ptp4l0-21swapper/123:15:021
114091290,0ptp4l0-21swapper/121:27:381
114091290,0ptp4l0-21swapper/100:27:251
114091290,0ptp4l0-21swapper/022:26:390
114091280,0ptp4l0-21swapper/623:21:596
114091280,0ptp4l0-21swapper/523:41:085
114091280,0ptp4l0-21swapper/523:13:265
114091280,0ptp4l0-21swapper/500:30:205
114091280,0ptp4l0-21swapper/123:01:461
114091280,0ptp4l0-21swapper/122:35:201
114091280,0ptp4l0-21swapper/122:34:381
114091280,0ptp4l0-21swapper/122:11:131
114091280,0ptp4l0-21swapper/121:35:231
114091280,0ptp4l0-21swapper/023:07:220
114091280,0ptp4l0-21swapper/022:07:190
114091270,0ptp4l0-21swapper/622:21:426
114091270,0ptp4l0-21swapper/523:56:415
114091270,0ptp4l0-21swapper/520:15:005
114091270,0ptp4l0-21swapper/500:36:515
114091270,0ptp4l0-21swapper/421:37:374
114091270,0ptp4l0-21swapper/123:43:501
114091270,0ptp4l0-21swapper/123:13:071
114091270,0ptp4l0-21swapper/122:53:521
114091270,0ptp4l0-21swapper/121:57:421
114091270,0ptp4l0-21swapper/121:33:461
114091270,0ptp4l0-21swapper/121:16:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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