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2025-07-04 - 02:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jul 03, 2025 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12482992914,14cyclictest0-21swapper/110:00:231
1248299230,5cyclictest0-21swapper/112:35:151
12482992221,1cyclictest14619-21mii-tool11:55:161
1248299220,21cyclictest893-21systemd-logind11:29:071
12486992113,7cyclictest0-21swapper/209:55:142
12482992118,2cyclictest0-21swapper/108:29:291
12482992113,4cyclictest0-21swapper/107:24:101
1248299210,20cyclictest0-21swapper/107:51:401
1247799215,15cyclictest11513-21mii-tool09:00:170
12477992119,1cyclictest9-21ksoftirqd/007:53:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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