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2024-09-07 - 16:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Sep 07, 2024 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2559099428427,1cyclictest2265-21kworker/0:208:06:030
2559099426425,1cyclictest2874-21kworker/0:010:14:010
2559099425423,1cyclictest2265-21kworker/0:207:31:030
2559899328311,14cyclictest21135-21kworker/1:111:45:021
2559899325323,0cyclictest0-21swapper/107:29:031
2560299323323,0cyclictest0-21swapper/207:29:032
2560299315311,2cyclictest0-21swapper/211:45:022
2559899308306,1cyclictest21135-21kworker/1:109:42:021
2560299305300,5cyclictest0-21swapper/210:41:022
2559899304301,1cyclictest0-21swapper/108:06:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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