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2024-07-27 - 03:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 26, 2024 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
976999399395,0cyclictest0-21swapper/208:38:022
976799396394,1cyclictest0-21swapper/008:38:030
976999387374,13cyclictest21089-21kworker/2:208:01:032
976999376374,0cyclictest0-21swapper/212:17:032
976999374374,0cyclictest0-21swapper/210:46:022
976999369367,1cyclictest21089-21kworker/2:208:06:022
976899366364,1cyclictest23793-21kworker/1:008:38:021
976799365363,1cyclictest18444-21kworker/0:011:18:020
976999364362,1cyclictest9758-21kworker/2:012:22:022
976899362359,2cyclictest0-21swapper/108:01:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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