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2024-05-23 - 20:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu May 23, 2024 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1712899429427,2cyclictest0-21swapper/210:46:022
1712899421420,1cyclictest0-21swapper/210:09:032
1712899413400,13cyclictest18632-21kworker/2:008:01:022
1712899397384,13cyclictest18632-21kworker/2:008:38:032
1712499355343,11cyclictest24471-21kworker/1:010:46:021
1712499349347,2cyclictest24471-21kworker/1:010:09:021
1712499333330,2cyclictest0-21swapper/108:01:021
1712499316315,0cyclictest0-21swapper/108:38:021
17128993130,310cyclictest0-21swapper/211:29:582
17124993101,1cyclictest0-21swapper/109:58:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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