You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-01-22 - 12:03
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 22, 2025 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20172992213,4cyclictest0-21swapper/119:19:481
20178992117,3cyclictest28-21ksoftirqd/219:30:012
20178992117,3cyclictest0-21swapper/223:13:352
2016899210,18cyclictest0-21swapper/020:45:480
2017899204,15cyclictest0-21swapper/222:30:152
20172992014,3cyclictest0-21swapper/119:47:271
20168992016,1cyclictest0-21swapper/023:40:160
2016899200,19cyclictest823-21systemd-network00:34:060
2017899192,16cyclictest0-21swapper/219:38:312
2017899190,18cyclictest28-21ksoftirqd/223:59:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional