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2025-12-13 - 20:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Dec 13, 2025 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1981499252,22cyclictest0-21swapper/212:01:012
1981499252,1cyclictest0-21swapper/207:58:262
1981299258,14cyclictest0-21swapper/008:23:150
19814992316,2cyclictest28471-21latency_hist07:25:012
19814992213,3cyclictest20691-21cpuspeed_turbos09:07:092
1981499221,15cyclictest0-21swapper/208:33:162
1981499210,3cyclictest3989-21H222:02:192
1981499210,2cyclictest3989-21H222:02:192
19813992117,3cyclictest27819-21grep10:17:101
19813992117,3cyclictest0-21swapper/110:55:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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