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2024-10-13 - 09:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Oct 13, 2024 00:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3349992313,0cyclictest0-21swapper/221:54:342
334799230,23cyclictest0-21swapper/020:05:150
334999216,14cyclictest0-21swapper/222:36:402
334899214,16cyclictest0-21swapper/121:28:241
3348992118,2cyclictest30548-21wc19:55:201
3349992014,5cyclictest0-21swapper/219:45:112
334999201,16cyclictest0-21swapper/223:10:042
334899203,2cyclictest17622-21ntp_kernel_err22:25:171
3348992016,3cyclictest0-21swapper/120:23:131
334799205,14cyclictest0-21swapper/023:36:470
334799201,18cyclictest9419-21nfsd420:15:170
334999192,16cyclictest14916-21cstates23:20:132
3349991914,3cyclictest0-21swapper/200:08:342
334999191,16cyclictest7474-21grep23:05:162
334999190,17cyclictest0-21swapper/200:15:172
3348991916,2cyclictest7376-21if_enp1s019:15:161
3348991916,2cyclictest7376-21if_enp1s019:15:151
334899191,3cyclictest0-21swapper/122:41:191
334899190,2cyclictest4528-21H212:26:331
334999182,1cyclictest194082chrt21:30:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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