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2025-03-24 - 01:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Mar 23, 2025 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
60299245,16cyclictest9628-21cron07:25:012
59899240,19cyclictest16515-21munin-run10:45:000
60299230,18cyclictest0-21swapper/209:50:122
60299220,18cyclictest0-21swapper/211:05:002
599992214,4cyclictest0-21swapper/109:32:351
598992015,2cyclictest10285-21systemctl07:25:010
60299190,2cyclictest4536-21H212:26:332
60299190,17cyclictest4528-21H212:26:332
60299190,16cyclictest4528-21H212:26:332
59999193,15cyclictest28402-21kernelversion10:00:171
59999193,15cyclictest21-21ksoftirqd/111:28:501
59999193,15cyclictest0-21swapper/110:48:101
59999192,2cyclictest8164-21cat10:30:001
59999192,2cyclictest15408-21nfsd410:40:171
59999191,17cyclictest4861-21grep09:10:191
59999190,16cyclictest4581-21H212:26:331
59999190,15cyclictest0-21swapper/107:11:221
59899192,16cyclictest24628-21cut11:00:220
59899192,11cyclictest31993-21munin-run11:20:000
59899192,11cyclictest25267-21/usr/sbin/munin07:55:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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