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2025-07-02 - 12:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 02, 2025 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29756993129,2cyclictest0-21swapper/221:17:482
29756993129,2cyclictest0-21swapper/221:07:542
29756993129,2cyclictest0-21swapper/221:07:542
29756993029,0cyclictest0-21swapper/221:14:582
29756993028,2cyclictest0-21swapper/200:37:062
29756992928,0cyclictest0-21swapper/223:46:402
2975699284,14cyclictest0-21swapper/220:30:172
29756992827,0cyclictest0-21swapper/223:09:062
29756992718,0cyclictest0-21swapper/220:43:422
29756992717,10cyclictest0-21swapper/220:54:192
29756992716,0cyclictest0-21swapper/220:46:082
29756992617,0cyclictest0-21swapper/222:54:142
29756992617,0cyclictest0-21swapper/221:24:242
29756992617,0cyclictest0-21swapper/220:09:472
29756992616,10cyclictest0-21swapper/222:40:522
2975399264,18cyclictest32502-21cat19:15:020
29756992515,10cyclictest0-21swapper/222:19:282
29756992412,10cyclictest0-21swapper/222:30:242
2975399247,2cyclictest23339-21grep21:50:140
2975699230,23cyclictest0-21swapper/223:32:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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