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2024-07-27 - 06:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jul 27, 2024 00:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
953421680,9sleep01018499cyclictest20:15:310
1176911610,14ptp4l0-21swapper/119:05:011
1176911500,7ptp4l0-21swapper/019:08:580
1176911480,18ptp4l0-21swapper/319:09:433
1176911120,16ptp4l0-21swapper/219:09:502
10186996756,7cyclictest33-21ksoftirqd/219:45:122
117691640,8ptp4l0-21swapper/200:04:482
117691630,2ptp4l0-21swapper/121:08:011
117691630,11ptp4l0-21swapper/220:10:342
117691620,2ptp4l0-21swapper/220:46:382
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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