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2024-03-01 - 01:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Feb 29, 2024 12:46:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1176911710,14ptp4l0-21swapper/007:08:020
1176911660,10ptp4l0-21swapper/107:05:161
1176911090,9ptp4l0-21swapper/207:05:532
1176911080,31ptp4l216-21systemd-journal07:07:153
551981030,15rtkit-daemon117691ptp4l11:16:153
117691760,3ptp4l401ktimersoftd/308:30:123
117691760,3ptp4l401ktimersoftd/308:30:123
117691760,2ptp4l0-21swapper/010:06:080
117691740,3ptp4l1185-21lldpd07:45:463
117691720,2ptp4l0-21swapper/009:42:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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