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2025-05-12 - 23:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon May 12, 2025 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2689521340,3sleep32099599cyclictest08:30:213
2847191630,3ptp4l24340-21df09:35:160
2847191620,3ptp4l0-21swapper/010:10:280
2847191610,4ptp4l0-21swapper/009:40:160
2847191600,3ptp4l26027-21/usr/sbin/munin08:30:161
2847191590,5ptp4l0-21swapper/310:35:083
2847191590,4ptp4l1306-21/usr/sbin/munin07:35:211
39122580,5sleep22099499cyclictest07:40:212
2847191580,4ptp4l0-21swapper/107:30:301
2847191580,4ptp4l0-21swapper/012:11:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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