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2024-06-14 - 23:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jun 14, 2024 12:46:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1176911750,12ptp4l0-21swapper/107:05:101
1176911700,60ptp4l0-21swapper/207:07:072
1176911650,16ptp4l0-21swapper/307:08:093
1176911450,56ptp4l0-21swapper/007:06:440
1176911050,7ptp4l0-21swapper/107:10:011
300702720,8sleep3398599cyclictest09:15:363
117691690,2ptp4l0-21swapper/207:20:342
117691650,1ptp4l0-21swapper/112:08:491
117691640,1ptp4l0-21swapper/107:49:071
117691630,2ptp4l0-21swapper/007:30:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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