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2024-09-17 - 00:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Sep 16, 2024 12:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1176911830,7ptp4l0-21swapper/307:08:043
1176911650,15ptp4l0-21swapper/007:07:200
3050021610,4sleep0108199cyclictest08:10:320
1176911530,15ptp4l0-21swapper/207:09:082
1176911500,14ptp4l0-21swapper/107:09:321
166622850,5sleep341-21ksoftirqd/311:10:153
117691670,5ptp4l8416-21/usr/sbin/munin08:35:322
1084996652,6cyclictest41-21ksoftirqd/308:20:113
117691650,5ptp4l14256-21sed07:35:270
117691640,1ptp4l0-21swapper/207:21:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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