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2024-04-24 - 08:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Apr 24, 2024 00:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1030222180,8sleep10-21swapper/119:05:241
1176911720,14ptp4l0-21swapper/219:05:082
1176911670,17ptp4l0-21swapper/019:08:360
1176911260,14ptp4l0-21swapper/319:05:463
317482710,8sleep11200099cyclictest23:20:291
117691680,2ptp4l0-21swapper/019:35:240
117691670,4ptp4l12478-21diskstats19:10:160
117691660,2ptp4l0-21swapper/021:50:240
117691640,2ptp4l0-21swapper/219:25:152
117691630,2ptp4l0-21swapper/021:40:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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