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2023-10-05 - 00:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Oct 04, 2023 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
60021850,8sleep21952199cyclictest08:45:372
60021850,8sleep21952199cyclictest08:45:362
1176911670,10ptp4l0-21swapper/107:08:161
1176911510,9ptp4l0-21swapper/007:05:330
1176911370,8ptp4l0-21swapper/207:07:042
1176911280,12ptp4l4815-21rs:main3
117691810,29ptp4l1159-21snmpd08:10:412
117691790,2ptp4l0-21swapper/112:21:221
117691740,2ptp4l0-21swapper/211:48:122
117691740,28ptp4l1185-21lldpd10:15:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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