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2023-12-03 - 12:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot1.osadl.org (updated Sun Dec 03, 2023 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2798721970,6sleep24813-21in:imuxsock19:05:372
1176911840,16ptp4l0-21swapper/019:05:520
1176911590,7ptp4l0-21swapper/119:08:021
1176911560,9ptp4l0-21swapper/319:09:493
270221460,4sleep22873599cyclictest20:30:402
265542990,3sleep3216-21systemd-journal22:39:593
117691750,2ptp4l0-21swapper/123:12:161
117691710,2ptp4l0-21swapper/123:39:041
117691680,8ptp4l1159-21snmpd23:00:302
117691680,8ptp4l1159-21snmpd23:00:302
117691680,2ptp4l0-21swapper/100:16:071
117691680,15ptp4l0-21swapper/221:45:042
28734996736,10cyclictest25-21ksoftirqd/119:10:201
28734996733,22cyclictest25-21ksoftirqd/122:50:161
117691670,11ptp4l0-21swapper/122:35:301
117791660,22getstats0-21swapper/122:13:061
117691660,2ptp4l0-21swapper/222:54:382
117691650,5ptp4l1185-21lldpd21:27:002
117691650,5ptp4l1185-21lldpd20:38:012
117691650,5ptp4l1185-21lldpd19:49:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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