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2026-02-09 - 06:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot1.osadl.org (updated Mon Feb 09, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2094521690,6sleep3683199cyclictest00:15:273
63752830,3sleep36380-21switchtime21:25:273
682999679,16cyclictest17112-21iostat21:50:181
682999668,14cyclictest25968-21/usr/sbin/munin22:10:121
682999645,16cyclictest14806-21irqrtprio20:35:171
175182640,2sleep017523-21irqrtprio23:00:180
682999639,10cyclictest30325-21latency_hist20:00:011
682999637,11cyclictest17169-21cut20:40:191
134491630,5ptp4l0-21swapper/023:50:190
682999627,11cyclictest2776-21sed23:40:011
6829996213,11cyclictest25384-21chrt23:15:361
6829996112,12cyclictest22944-21chrt20:51:461
6829996110,16cyclictest16499-21mv00:06:031
682999609,10cyclictest18844-21unixbench_singl00:10:271
682999608,10cyclictest25337-21sed19:49:591
682999606,10cyclictest0-21swapper/100:35:261
6829996010,12cyclictest21297-21sed23:10:001
682999597,20cyclictest11953-21grep21:40:131
6829995911,9cyclictest22394-21sed23:10:221
134491590,4ptp4l0-21swapper/100:20:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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