You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-09-19 - 22:57
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Sep 19, 2024 12:46:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1092121600,7sleep21149599cyclictest08:15:272
825991143121,10phc2sys0-21swapper/307:06:113
2669521380,8sleep11149499cyclictest08:50:151
825591800,2ptp4l391rcuc/307:35:243
109502807,61sleep20-21swapper/207:06:402
825591700,1ptp4l401ktimersoftd/312:20:163
825591650,1ptp4l401ktimersoftd/312:34:253
825591630,1ptp4l401ktimersoftd/307:25:373
128862630,3sleep10-21swapper/111:45:201
825591620,1ptp4l401ktimersoftd/312:25:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional