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2025-07-04 - 02:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Jul 03, 2025 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
283572224197,18sleep30-21swapper/307:05:593
285052206174,22sleep10-21swapper/107:07:541
286682202169,22sleep00-21swapper/007:09:580
286722199165,23sleep20-21swapper/207:10:002
273221610,3sleep00-21swapper/011:50:230
1449821240,2sleep00-21swapper/010:00:230
316232550,4sleep0101ktimersoftd/010:35:250
136991540,1ptp4l401ktimersoftd/307:40:393
254522520,4sleep2321ktimersoftd/208:10:002
254522520,4sleep2321ktimersoftd/208:10:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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