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2025-07-15 - 12:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Jul 15, 2025 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191237170,22phc2sys0-21swapper/319:05:423
95162207174,22sleep20-21swapper/219:08:462
95932205171,23sleep10-21swapper/119:09:461
95192203170,22sleep00-21swapper/019:08:480
226921390,4sleep21006499cyclictest20:00:212
59298550,9rtkit-daemon0-21swapper/219:43:262
136991500,1ptp4l391rcuc/323:52:303
59298450,2rtkit-daemon0-21swapper/323:03:253
59298440,9rtkit-daemon0-21swapper/222:06:462
59298430,9rtkit-daemon0-21swapper/322:47:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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