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2026-05-21 - 06:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu May 21, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206173,22phc2sys0-21swapper/319:07:023
91762205171,22sleep20-21swapper/219:06:072
92382204171,22sleep10-21swapper/119:06:551
92372202169,22sleep00-21swapper/019:06:530
935621210,2sleep30-21swapper/322:30:193
1393911130,1ptp4l17112-21cpuspeed_turbos19:25:123
134372690,1sleep00-21swapper/020:25:120
9772996022,3cyclictest41-21ksoftirqd/322:00:213
9770996016,4cyclictest25-21ksoftirqd/120:40:251
9772995927,8cyclictest41-21ksoftirqd/320:30:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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