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2025-03-20 - 02:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Mar 19, 2025 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191234167,23phc2sys0-21swapper/307:07:253
309512208174,22sleep10-21swapper/107:08:041
308012205171,23sleep00-21swapper/007:06:060
307772202169,22sleep20-21swapper/207:05:482
136991630,1ptp4l401ktimersoftd/309:14:303
136991610,1ptp4l401ktimersoftd/308:17:253
67102600,6sleep13140299cyclictest07:25:161
67102600,6sleep13140299cyclictest07:25:161
31403996030,4cyclictest33-21ksoftirqd/211:11:542
31403996026,6cyclictest33-21ksoftirqd/209:40:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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