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2024-07-21 - 22:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jul 21, 2024 12:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8255912020,6ptp4l401ktimersoftd/307:05:223
3236521850,7sleep2470299cyclictest07:15:432
3236521850,7sleep2470299cyclictest07:15:422
3237021640,8sleep3470399cyclictest08:36:273
2950721540,6sleep1470199cyclictest09:40:211
2092021300,8sleep0470099cyclictest07:11:230
2181321240,4sleep121821-21spawn07:12:531
470399776,13cyclictest10151-21grep07:17:553
470399776,13cyclictest10151-21grep07:17:543
4700997661,8cyclictest9-21ksoftirqd/009:00:100
4700997661,8cyclictest9-21ksoftirqd/009:00:100
4700997561,8cyclictest9-21ksoftirqd/011:00:160
163292730,5sleep216335-21spawn07:11:292
94382720,6sleep19411-21sh07:15:541
94382720,6sleep19411-21sh07:15:541
470399694,12cyclictest17009-21od07:21:023
4700996856,6cyclictest9-21ksoftirqd/012:15:090
178982680,8sleep2470299cyclictest08:05:312
59962660,4sleep05997-21hwlatdetect10:00:150
4700996654,6cyclictest9-21ksoftirqd/011:15:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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