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2025-05-14 - 23:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed May 14, 2025 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191207172,23phc2sys0-21swapper/307:06:023
167372206172,22sleep20-21swapper/207:05:582
168532204170,22sleep00-21swapper/007:07:290
167032202167,23sleep10-21swapper/107:05:331
136991690,1ptp4l401ktimersoftd/310:37:273
132891600,2getstats0-21swapper/310:00:123
17232550,7sleep11734099cyclictest07:45:041
17232550,7sleep11734099cyclictest07:45:041
136991550,1ptp4l391rcuc/311:37:463
320772510,2sleep00-21swapper/007:40:180
17342994943,3cyclictest16005-21cron08:15:003
136991470,1ptp4l401ktimersoftd/311:53:483
59298430,9rtkit-daemon0-21swapper/111:12:491
17339994237,3cyclictest3765-21cron12:25:000
136991420,0ptp4l401ktimersoftd/310:20:453
136991420,0ptp4l401ktimersoftd/308:40:523
17342994136,3cyclictest32574-21cron08:50:003
17342994136,3cyclictest32574-21cron08:50:003
132891410,7getstats1734299cyclictest08:00:113
132891410,1getstats0-21swapper/309:00:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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