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2025-07-14 - 21:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jul 14, 2025 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191232169,51phc2sys0-21swapper/307:08:463
43402203170,22sleep20-21swapper/207:08:532
43952198163,23sleep00-21swapper/007:09:350
41892194160,22sleep10-21swapper/107:06:551
1204821260,5sleep1472499cyclictest09:40:151
144152560,2sleep10-21swapper/107:30:141
136991560,1ptp4l401ktimersoftd/312:09:453
136991560,1ptp4l401ktimersoftd/308:06:453
136991560,1ptp4l401ktimersoftd/307:30:043
136991550,1ptp4l401ktimersoftd/309:45:543
181602530,1sleep10-21swapper/112:05:251
136991530,1ptp4l401ktimersoftd/311:48:053
75642510,2sleep00-21swapper/007:15:200
443124734,8sleep10-21swapper/107:10:001
4725994639,4cyclictest28379-21turbostat.cron10:14:592
4725994611,4cyclictest33-21ksoftirqd/210:20:002
136991460,1ptp4l401ktimersoftd/311:24:063
4725994539,4cyclictest29779-21dump-pmu-power11:24:592
472599447,7cyclictest33-21ksoftirqd/209:00:012
4724994424,17cyclictest25-21ksoftirqd/110:44:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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