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2024-07-27 - 07:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 27, 2024 00:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8255912020,7ptp4l401ktimersoftd/319:06:443
109672156105,38sleep10-21swapper/119:05:381
50121330,2sleep30-21swapper/300:30:113
1116829171,10sleep00-21swapper/019:08:170
7782890,8sleep31159099cyclictest23:20:203
57698860,15rtkit-daemon0-21swapper/219:08:192
825791680,8getstats1159099cyclictest23:34:363
164562670,4sleep0101ktimersoftd/019:20:130
11590996455,5cyclictest41-21ksoftirqd/322:55:123
825591620,1ptp4l401ktimersoftd/323:06:503
825591550,1ptp4l401ktimersoftd/319:41:323
205182500,5sleep233-21ksoftirqd/221:45:082
234842484,5sleep2121rcu_preempt20:40:342
825591460,1ptp4l401ktimersoftd/321:22:513
11587994540,3cyclictest9-21ksoftirqd/021:59:590
1159099442,39cyclictest9140-21cron23:40:003
11588994437,5cyclictest25-21ksoftirqd/123:45:001
825791430,2getstats0-21swapper/323:19:373
124932430,4sleep01158799cyclictest20:20:110
11589994323,5cyclictest33-21ksoftirqd/200:14:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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