You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-01-18 - 11:45
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Sat Jan 18, 2025 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134791206172,22phc2sys0-21swapper/319:06:333
319862205171,22sleep20-21swapper/219:09:292
319622201168,22sleep00-21swapper/019:09:120
297952200167,22sleep10-21swapper/119:05:031
429021630,6sleep13232099cyclictest19:15:261
32322997728,4cyclictest41-21ksoftirqd/321:30:013
32321996933,4cyclictest33-21ksoftirqd/200:29:592
32322996031,4cyclictest41-21ksoftirqd/323:18:183
32321996023,9cyclictest33-21ksoftirqd/223:15:162
32321995927,9cyclictest33-21ksoftirqd/222:00:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional