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2026-05-14 - 00:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Wed May 13, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
319692203169,22sleep00-21swapper/007:09:540
138591203168,23phc2sys0-21swapper/307:08:243
316372201167,22sleep20-21swapper/207:05:432
316432200167,22sleep10-21swapper/107:05:451
2319621180,2sleep30-21swapper/309:00:203
3197728264,10sleep20-21swapper/207:10:012
1385918162,10phc2sys0-21swapper/307:10:003
57382650,3sleep20-21swapper/211:40:182
59292610,2sleep30-21swapper/307:20:193
276702610,4sleep3391rcuc/312:25:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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