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2025-12-12 - 13:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Fri Dec 12, 2025 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
427791204170,22phc2sys0-21swapper/319:06:593
263202204170,23sleep20-21swapper/219:05:342
266442203169,22sleep00-21swapper/019:09:380
265572201166,23sleep10-21swapper/119:08:301
427791162122,13phc2sys0-21swapper/319:10:013
427291650,1ptp4l401ktimersoftd/319:21:323
427291590,1ptp4l401ktimersoftd/321:26:073
427291580,1ptp4l401ktimersoftd/323:00:173
227432580,2sleep20-21swapper/221:10:182
108242540,5sleep32696999cyclictest19:40:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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