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2024-09-12 - 07:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Thu Sep 12, 2024 00:46:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1299911750,6ptp4l401ktimersoftd/319:05:493
564981330,106rtkit-daemon1343-21mactelnetd19:06:480
15702999883,8cyclictest41-21ksoftirqd/319:25:123
15702999883,8cyclictest41-21ksoftirqd/319:25:123
15702999781,9cyclictest41-21ksoftirqd/323:35:123
15702999683,7cyclictest41-21ksoftirqd/320:55:103
15702999683,7cyclictest41-21ksoftirqd/320:55:093
15702999682,8cyclictest41-21ksoftirqd/322:05:113
15702999580,8cyclictest41-21ksoftirqd/321:20:103
21912940,8sleep01569999cyclictest19:50:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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