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2025-06-19 - 08:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Thu Jun 19, 2025 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134791229167,51phc2sys0-21swapper/319:07:513
59382203170,22sleep10-21swapper/119:06:581
59592201169,21sleep20-21swapper/219:07:162
59272201166,23sleep00-21swapper/019:06:490
1347918261,11phc2sys0-21swapper/319:10:013
240182770,2sleep00-21swapper/020:50:150
173872680,7sleep2664499cyclictest19:30:222
134991620,1ptp4l401ktimersoftd/323:05:113
6641995928,7cyclictest25-21ksoftirqd/121:00:001
664099595,6cyclictest6141-21latency_hist21:20:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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