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2024-12-11 - 16:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot5.osadl.org (updated Wed May 05, 2021 00:45:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3027099372,30cyclictest9529-21kworker/0:122:19:520
3027099371,31cyclictest18330-21kworker/0:221:05:400
3027099371,31cyclictest18330-21kworker/0:221:05:400
3027099363,29cyclictest16345-21kworker/0:020:22:040
3027099363,29cyclictest16345-21kworker/0:020:22:040
3027099362,29cyclictest2216-21kworker/0:321:22:560
3027099362,29cyclictest2216-21kworker/0:321:22:560
3027099362,29cyclictest19024-21kworker/0:122:39:570
3027099362,29cyclictest19024-21kworker/0:122:39:560
3027099361,30cyclictest16345-21kworker/0:020:25:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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