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2022-07-05 - 02:28

x86 Intel Atom E3950 @1600 MHz, Linux 4.19.182-rt74 (Profile)

Latency plot of system in rack #d, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot5.osadl.org (updated Wed May 05, 2021 00:45:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3027099372,30cyclictest9529-21kworker/0:122:19:520
3027099371,31cyclictest18330-21kworker/0:221:05:400
3027099371,31cyclictest18330-21kworker/0:221:05:400
3027099363,29cyclictest16345-21kworker/0:020:22:040
3027099363,29cyclictest16345-21kworker/0:020:22:040
3027099362,29cyclictest2216-21kworker/0:321:22:560
3027099362,29cyclictest2216-21kworker/0:321:22:560
3027099362,29cyclictest19024-21kworker/0:122:39:570
3027099362,29cyclictest19024-21kworker/0:122:39:560
3027099361,30cyclictest16345-21kworker/0:020:25:490
3027099361,30cyclictest13831-21kworker/0:319:11:040
3027099361,30cyclictest13831-21kworker/0:319:11:040
3027099361,29cyclictest26271-21kworker/0:123:43:570
3027099352,29cyclictest13150-21kworker/0:123:51:360
3027099352,28cyclictest19912-21kworker/0:220:47:440
3027099351,29cyclictest31951-21kworker/0:022:07:250
3027099351,29cyclictest30402-21kworker/0:221:53:560
3027099351,29cyclictest23616-21kworker/0:022:21:290
3027099351,29cyclictest11639-21kworker/0:122:03:290
3027099351,29cyclictest10203-21kworker/0:321:39:240
3027099345,25cyclictest9529-21kworker/0:122:11:320
3027099344,26cyclictest18241-21kworker/0:323:57:370
3027099342,28cyclictest15463-21kworker/0:119:47:170
3027099341,29cyclictest1048-21kworker/0:000:23:440
3027099341,29cyclictest1048-21kworker/0:000:23:440
3027099341,28cyclictest675-21kworker/0:020:56:520
3027099341,28cyclictest15464-21kworker/0:219:24:000
3027099341,28cyclictest10677-21kworker/0:200:33:200
3027099340,29cyclictest851-21kworker/0:020:02:210
3027099340,29cyclictest15463-21kworker/0:119:44:200
3027099334,26cyclictest2888-21kworker/0:223:36:520
3027099331,28cyclictest2888-21kworker/0:223:29:210
3027099331,28cyclictest23616-21kworker/0:022:26:560
3027099330,29cyclictest13831-21kworker/0:319:18:170
3027099330,29cyclictest13831-21kworker/0:319:18:170
3026899333,28cyclictest27018-21kworker/0:019:30:360
3026899324,26cyclictest851-21kworker/0:020:05:560
3026899324,26cyclictest851-21kworker/0:020:05:560
3026899323,27cyclictest9277-21kworker/0:323:30:280
3026899323,27cyclictest4853-21kworker/0:221:31:080
3026899322,28cyclictest9336-21kworker/0:020:39:560
3026899322,28cyclictest9336-21kworker/0:020:39:560
3026899322,28cyclictest19769-21kworker/0:023:16:370
3026899322,28cyclictest19769-21kworker/0:023:16:360
3026899322,28cyclictest18330-21kworker/0:221:05:040
3026899322,28cyclictest1100-21kworker/0:323:11:050
3027099314,25cyclictest1191-21kworker/0:120:32:360
3026899313,25cyclictest1048-21kworker/0:000:25:410
3026899313,25cyclictest1048-21kworker/0:000:25:400
3026899312,27cyclictest675-21kworker/0:020:50:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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