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2024-11-12 - 23:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot7.osadl.org (updated Wed Mar 24, 2021 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15568622234178,48sleep20-21swapper/219:08:562
15569302223174,41sleep00-21swapper/019:09:460
15565922222184,31sleep30-21swapper/319:05:313
15568512218179,31sleep10-21swapper/119:08:461
159848221850,2sleep30-21swapper/320:00:023
181813421730,4sleep0155720990cyclictest00:25:140
181813421730,4sleep0155720990cyclictest00:25:140
173382521700,3sleep30-21swapper/322:45:043
156229321610,3sleep30-21swapper/319:15:053
156229321610,3sleep30-21swapper/319:15:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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