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2024-05-22 - 01:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot8.osadl.org (updated Thu Feb 06, 2020 10:49:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121028690315,23cyclictest1284161-21munin-run08:40:011
121028690315,23cyclictest1284161-21munin-run08:40:001
121028590315,13cyclictest1428017-21perf11:35:010
1210286902514,6cyclictest1424479-21ptp4l-jitter11:30:031
121028690251,21cyclictest393-21systemd-journal12:40:011
121028690251,21cyclictest1612-21systemd-logind07:40:001
1210285902419,3cyclictest1358156-21munin-run10:10:010
121028590241,2cyclictest111rcu_preempt11:15:000
121028590241,11cyclictest1304765-21latency_hist09:05:010
1210287902319,2cyclictest0-21swapper/211:20:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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