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2023-06-09 - 13:15

x86 Intel Core i7-8565U @1800 MHz, Linux 6.0.0-rt11 (Profile)

Latency plot of system in rack #e, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot0.osadl.org (updated Fri Jun 09, 2023 00:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1429399375,31cyclictest6741-21apt-config22:43:414
14290992928,1cyclictest0-21swapper/100:25:581
14290992927,1cyclictest0-21swapper/100:00:121
14296992827,1cyclictest0-21swapper/723:49:187
1429499286,21cyclictest25459-21lsb_release22:10:245
14290992826,1cyclictest0-21swapper/122:40:201
14290992825,1cyclictest161rcu_preempt23:43:051
14290992824,1cyclictest0-21swapper/100:10:581
14296992727,0cyclictest0-21swapper/721:46:567
14296992727,0cyclictest0-21swapper/700:23:377
14295992726,1cyclictest0-21swapper/623:26:386
14295992726,1cyclictest0-21swapper/623:14:536
14295992725,1cyclictest0-21swapper/600:17:256
14295992724,2cyclictest661rcuc/621:28:486
14294992721,2cyclictest12221-21lsb_release00:20:365
14290992726,1cyclictest0-21swapper/121:25:511
14290992724,2cyclictest702-21in:imklog23:45:521
14296992626,0cyclictest0-21swapper/721:15:027
14296992625,0cyclictest0-21swapper/723:37:247
14295992625,1cyclictest0-21swapper/623:30:526
14295992625,1cyclictest0-21swapper/623:09:176
14295992625,1cyclictest0-21swapper/600:00:126
1429599262,23cyclictest1-21systemd22:03:566
14294992624,2cyclictest32002-21lsb_release23:37:425
14290992625,1cyclictest0-21swapper/123:08:401
14290992625,1cyclictest0-21swapper/122:46:311
14290992625,1cyclictest0-21swapper/122:00:311
1428999260,24cyclictest4024-21gpgconf22:50:560
14296992525,0cyclictest0-21swapper/723:57:047
14296992523,1cyclictest741rcuc/721:00:287
14295992525,0cyclictest0-21swapper/623:22:366
14295992525,0cyclictest0-21swapper/621:38:166
14295992525,0cyclictest0-21swapper/621:24:326
14295992525,0cyclictest0-21swapper/600:24:396
14295992524,1cyclictest0-21swapper/622:58:466
14295992524,1cyclictest0-21swapper/621:33:426
14295992523,1cyclictest0-21swapper/622:24:446
14295992523,1cyclictest0-21swapper/621:08:126
14295992523,1cyclictest0-21swapper/600:39:146
14295992522,2cyclictest19578-21snmpd19:46:526
14294992521,1cyclictest161rcu_preempt21:45:155
14293992521,3cyclictest5125-21kworker/4:1+events21:15:104
14293992521,3cyclictest12189-21kworker/4:0+events21:41:494
14293992521,1cyclictest25072-21kworker/4:1+events23:26:504
14293992521,1cyclictest10331-21kworker/4:3+events22:08:144
14290992524,1cyclictest0-21swapper/122:58:471
14290992524,1cyclictest0-21swapper/121:05:291
14290992524,1cyclictest0-21swapper/100:38:461
14290992524,0cyclictest0-21swapper/121:44:461
14290992523,1cyclictest0-21swapper/122:26:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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