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2022-07-05 - 20:51

x86 Intel Core i7-8565U @1800 MHz, Linux 5.4.17-rt9 (Profile)

Latency plot of system in rack #e, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -n -p99 -i200 -h400 -a0-2 -t3 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot0.osadl.org (updated Tue Jul 05, 2022 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1733999340,33cyclictest0-21swapper/208:17:022
17339993333,0cyclictest0-21swapper/209:22:022
1733999330,33cyclictest0-21swapper/212:17:012
1733999330,33cyclictest0-21swapper/207:54:022
1733999330,32cyclictest0-21swapper/212:13:032
1733999330,32cyclictest0-21swapper/212:13:022
1733999330,32cyclictest0-21swapper/211:26:022
1733999330,32cyclictest0-21swapper/211:11:022
1733999330,32cyclictest0-21swapper/210:10:032
1733999330,32cyclictest0-21swapper/209:17:032
1733299330,33cyclictest0-21swapper/107:26:021
17339993232,0cyclictest0-21swapper/212:07:022
17339993232,0cyclictest0-21swapper/211:53:022
17339993232,0cyclictest0-21swapper/211:40:022
17339993232,0cyclictest0-21swapper/211:36:022
17339993232,0cyclictest0-21swapper/210:55:022
17339993232,0cyclictest0-21swapper/210:46:032
17339993232,0cyclictest0-21swapper/210:02:022
17339993232,0cyclictest0-21swapper/208:58:022
1733999320,32cyclictest0-21swapper/210:53:022
1733999320,32cyclictest0-21swapper/208:40:032
1733999320,32cyclictest0-21swapper/208:22:022
1733999320,32cyclictest0-21swapper/207:57:032
1733999320,32cyclictest0-21swapper/207:46:022
1733999320,0cyclictest0-21swapper/209:32:022
1733999320,0cyclictest0-21swapper/209:25:022
1733999320,0cyclictest0-21swapper/208:00:032
1733299320,32cyclictest0-21swapper/107:22:021
1733299320,0cyclictest0-21swapper/107:14:021
17339993131,0cyclictest0-21swapper/212:39:032
17339993131,0cyclictest0-21swapper/212:25:022
17339993131,0cyclictest0-21swapper/212:02:032
17339993131,0cyclictest0-21swapper/211:22:022
17339993131,0cyclictest0-21swapper/210:34:022
17339993131,0cyclictest0-21swapper/210:25:012
17339993131,0cyclictest0-21swapper/210:09:022
17339993131,0cyclictest0-21swapper/209:58:022
17339993131,0cyclictest0-21swapper/209:43:032
17339993131,0cyclictest0-21swapper/209:35:022
17339993131,0cyclictest0-21swapper/209:02:022
17339993131,0cyclictest0-21swapper/208:07:032
17339993030,0cyclictest0-21swapper/212:33:032
17339993030,0cyclictest0-21swapper/211:46:022
17339993030,0cyclictest0-21swapper/211:09:012
17339992929,0cyclictest0-21swapper/211:34:022
17339992929,0cyclictest0-21swapper/211:19:022
17339992929,0cyclictest0-21swapper/210:21:032
17339992929,0cyclictest0-21swapper/210:15:022
17339992929,0cyclictest0-21swapper/209:51:012
17339992929,0cyclictest0-21swapper/209:14:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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