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2021-07-29 - 05:29

Intel(R) Core(TM) i5-8365UE CPU @ 1.60GHz, Linux 5.9.1-rt18 (Profile)

Latency plot of system in rack #e, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -p90 -i200 -h400 -a2-3 -t2 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackeslot1.osadl.org (updated Thu Jul 29, 2021 00:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1881190190,14cyclictest0-21swapper/321:55:303
1881190170,16cyclictest0-21swapper/319:49:483
1881190170,0cyclictest0-21swapper/300:20:413
18811901615,1cyclictest0-21swapper/319:20:043
18811901614,2cyclictest0-21swapper/321:21:013
18811901614,2cyclictest0-21swapper/320:24:443
18811901614,1cyclictest0-21swapper/319:40:013
1881190160,16cyclictest0-21swapper/321:17:523
1881190160,16cyclictest0-21swapper/319:26:323
1881190160,14cyclictest0-21swapper/323:12:043
1881190160,14cyclictest0-21swapper/323:01:083
1881190160,14cyclictest0-21swapper/321:28:523
1881190160,14cyclictest0-21swapper/321:14:453
1881190160,14cyclictest0-21swapper/321:07:403
1881190160,14cyclictest0-21swapper/321:02:553
1881190160,14cyclictest0-21swapper/320:52:383
1881190160,14cyclictest0-21swapper/319:34:343
1881190160,14cyclictest0-21swapper/319:16:523
1881190160,14cyclictest0-21swapper/300:13:403
1881190160,0cyclictest0-21swapper/320:10:323
18810901614,1cyclictest0-21swapper/220:45:152
18811901515,0cyclictest0-21swapper/300:00:503
18811901514,1cyclictest0-21swapper/323:53:233
18811901514,1cyclictest0-21swapper/321:50:003
18811901514,1cyclictest0-21swapper/320:36:043
18811901514,1cyclictest0-21swapper/320:27:193
18811901513,2cyclictest0-21swapper/323:16:453
18811901513,2cyclictest0-21swapper/300:15:133
18811901513,2cyclictest0-21swapper/300:07:243
1881190150,15cyclictest0-21swapper/323:40:473
1881190150,15cyclictest0-21swapper/323:33:073
1881190150,15cyclictest0-21swapper/323:26:063
1881190150,15cyclictest0-21swapper/323:21:073
1881190150,15cyclictest0-21swapper/323:05:113
1881190150,15cyclictest0-21swapper/322:57:023
1881190150,15cyclictest0-21swapper/322:46:363
1881190150,15cyclictest0-21swapper/322:35:133
1881190150,15cyclictest0-21swapper/322:06:383
1881190150,15cyclictest0-21swapper/321:48:283
1881190150,15cyclictest0-21swapper/321:42:103
1881190150,15cyclictest0-21swapper/321:30:283
1881190150,15cyclictest0-21swapper/320:55:483
1881190150,15cyclictest0-21swapper/320:18:323
1881190150,15cyclictest0-21swapper/319:51:143
1881190150,15cyclictest0-21swapper/319:10:163
1881190150,15cyclictest0-21swapper/300:38:023
1881190150,15cyclictest0-21swapper/300:27:423
1881190150,14cyclictest0-21swapper/320:31:163
1881190150,13cyclictest0-21swapper/322:25:583
1881190150,0cyclictest0-21swapper/323:56:273
1881190150,0cyclictest0-21swapper/323:46:203
1881190150,0cyclictest0-21swapper/323:36:593
1881190150,0cyclictest0-21swapper/322:50:093
1881190150,0cyclictest0-21swapper/322:41:363
1881190150,0cyclictest0-21swapper/322:33:013
1881190150,0cyclictest0-21swapper/322:21:193
1881190150,0cyclictest0-21swapper/322:15:023
1881190150,0cyclictest0-21swapper/322:11:563
1881190150,0cyclictest0-21swapper/322:04:083
1881190150,0cyclictest0-21swapper/320:47:563
1881190150,0cyclictest0-21swapper/320:40:493
1881190150,0cyclictest0-21swapper/320:05:443
1881190150,0cyclictest0-21swapper/319:57:023
1881190150,0cyclictest0-21swapper/319:40:113
18811901413,1cyclictest0-21swapper/300:30:043
1881190140,14cyclictest0-21swapper/321:35:373
1881190140,14cyclictest0-21swapper/320:00:593
18810901414,0cyclictest0-21swapper/223:05:252
18810901414,0cyclictest0-21swapper/222:51:262
18810901414,0cyclictest0-21swapper/222:07:282
18810901414,0cyclictest0-21swapper/221:05:482
18810901414,0cyclictest0-21swapper/220:05:302
18810901414,0cyclictest0-21swapper/200:29:482
18810901414,0cyclictest0-21swapper/200:02:082
18810901411,2cyclictest0-21swapper/200:05:182
1881090140,14cyclictest0-21swapper/223:57:012
1881090140,14cyclictest0-21swapper/223:51:242
1881090140,14cyclictest0-21swapper/223:49:302
1881090140,14cyclictest0-21swapper/223:41:372
1881090140,14cyclictest0-21swapper/223:37:402
1881090140,14cyclictest0-21swapper/223:31:172
1881090140,14cyclictest0-21swapper/223:25:502
1881090140,14cyclictest0-21swapper/223:21:092
1881090140,14cyclictest0-21swapper/223:15:062
1881090140,14cyclictest0-21swapper/223:10:132
1881090140,14cyclictest0-21swapper/223:02:532
1881090140,14cyclictest0-21swapper/222:35:442
1881090140,14cyclictest0-21swapper/222:27:072
1881090140,14cyclictest0-21swapper/222:20:362
1881090140,14cyclictest0-21swapper/222:17:172
1881090140,14cyclictest0-21swapper/222:10:442
1881090140,14cyclictest0-21swapper/222:00:262
1881090140,14cyclictest0-21swapper/221:56:032
1881090140,14cyclictest0-21swapper/221:50:052
1881090140,14cyclictest0-21swapper/221:45:392
1881090140,14cyclictest0-21swapper/221:40:012
1881090140,14cyclictest0-21swapper/221:35:012
1881090140,14cyclictest0-21swapper/221:30:302
1881090140,14cyclictest0-21swapper/221:26:162
1881090140,14cyclictest0-21swapper/221:20:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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