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2022-10-04 - 03:22

x86 Intel Core i5-8365UE @1600 MHz, Linux 5.19.0-rc7-rt7 (Profile)

Latency plot of system in rack #e, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp90 -i200 -h400 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackeslot1.osadl.org (updated Mon Oct 03, 2022 12:43:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1163751901714,2cyclictest1254968-21systemctl08:20:240
116375190170,2cyclictest1636932-21kthreadcore12:20:190
116375190170,1cyclictest1449573-21kthreadcore10:30:200
116375190170,0cyclictest0-21swapper/011:15:030
116375890160,15cyclictest1244841-21chrt08:15:083
116375790160,15cyclictest1209399-21chrt07:43:052
1163751901616,0cyclictest1476616-21ssh10:45:290
1163751901616,0cyclictest0-21swapper/008:45:200
1163751901614,1cyclictest1518974-21sh11:10:210
116375190160,2cyclictest1214025-21memory07:45:190
116375190160,15cyclictest1497619-21/usr/sbin/munin11:00:230
1163758901515,0cyclictest0-21swapper/309:55:203
116375890150,14cyclictest0-21swapper/312:30:223
1163757901515,0cyclictest0-21swapper/211:41:062
1163757901513,1cyclictest13230682chrt09:16:042
116375790150,14cyclictest1308069-21chrt09:09:142
116375790150,14cyclictest0-21swapper/212:29:552
116375790150,14cyclictest0-21swapper/212:09:372
116375790150,14cyclictest0-21swapper/212:04:462
116375790150,14cyclictest0-21swapper/211:20:452
116375790150,14cyclictest0-21swapper/211:06:192
116375790150,14cyclictest0-21swapper/210:40:182
116375790150,14cyclictest0-21swapper/209:42:092
116375290150,14cyclictest0-21swapper/112:18:401
116375290150,14cyclictest0-21swapper/111:52:261
116375290150,14cyclictest0-21swapper/111:32:401
116375290150,14cyclictest0-21swapper/109:35:171
1163751901513,1cyclictest1309160-21expr09:10:170
116375190151,14cyclictest1326791-21tail09:20:180
116375190150,1cyclictest1566577-21sed11:40:190
116375190150,1cyclictest1233564-21diskstats08:05:160
116375190150,1cyclictest0-21swapper/010:54:320
116375190150,15cyclictest1582729-21cron11:50:010
116375190150,15cyclictest1403525-21head10:05:170
116375190150,15cyclictest1351830-21ssh09:35:100
116375190150,15cyclictest1260716-21cut08:25:240
1163758901414,0cyclictest0-21swapper/311:10:083
1163758901414,0cyclictest0-21swapper/310:57:293
1163758901414,0cyclictest0-21swapper/310:04:333
1163758901414,0cyclictest0-21swapper/309:22:173
1163758901414,0cyclictest0-21swapper/309:14:323
1163758901414,0cyclictest0-21swapper/308:50:513
1163758901414,0cyclictest0-21swapper/308:41:223
1163758901414,0cyclictest0-21swapper/307:37:593
1163758901413,1cyclictest15547332sleep311:31:313
1163758901413,1cyclictest0-21swapper/309:02:083
116375890140,14cyclictest0-21swapper/312:18:523
116375890140,14cyclictest0-21swapper/312:02:113
116375890140,14cyclictest0-21swapper/311:00:513
116375890140,14cyclictest0-21swapper/310:50:023
116375890140,14cyclictest0-21swapper/310:38:373
116375890140,14cyclictest0-21swapper/309:46:493
116375890140,14cyclictest0-21swapper/309:43:023
116375890140,14cyclictest0-21swapper/309:28:563
116375890140,14cyclictest0-21swapper/309:28:563
116375890140,14cyclictest0-21swapper/308:59:503
116375890140,14cyclictest0-21swapper/308:00:153
116375890140,13cyclictest0-21swapper/312:20:153
116375890140,13cyclictest0-21swapper/310:30:183
116375890140,13cyclictest0-21swapper/309:30:023
116375890140,13cyclictest0-21swapper/308:05:063
116375890140,13cyclictest0-21swapper/307:40:203
116375890140,0cyclictest0-21swapper/312:28:443
116375890140,0cyclictest0-21swapper/312:11:513
116375890140,0cyclictest0-21swapper/311:17:253
116375890140,0cyclictest0-21swapper/310:29:413
116375890140,0cyclictest0-21swapper/310:17:173
116375890140,0cyclictest0-21swapper/310:08:473
116375890140,0cyclictest0-21swapper/309:52:473
116375890140,0cyclictest0-21swapper/309:16:323
116375890140,0cyclictest0-21swapper/308:25:143
1163757901414,0cyclictest0-21swapper/211:11:212
1163757901413,0cyclictest0-21swapper/212:22:482
116375790140,13cyclictest0-21swapper/212:35:392
116375790140,13cyclictest0-21swapper/212:18:522
116375790140,13cyclictest0-21swapper/211:56:142
116375790140,13cyclictest0-21swapper/211:45:022
116375790140,13cyclictest0-21swapper/211:35:172
116375790140,13cyclictest0-21swapper/211:30:522
116375790140,13cyclictest0-21swapper/211:17:152
116375790140,13cyclictest0-21swapper/211:01:372
116375790140,13cyclictest0-21swapper/210:56:522
116375790140,13cyclictest0-21swapper/210:46:042
116375790140,13cyclictest0-21swapper/210:37:422
116375790140,13cyclictest0-21swapper/210:32:222
116375790140,13cyclictest0-21swapper/210:26:112
116375790140,13cyclictest0-21swapper/210:21:212
116375790140,13cyclictest0-21swapper/210:15:262
116375790140,13cyclictest0-21swapper/210:10:292
116375790140,13cyclictest0-21swapper/210:07:152
116375790140,13cyclictest0-21swapper/209:59:002
116375790140,13cyclictest0-21swapper/209:53:332
116375790140,13cyclictest0-21swapper/209:45:562
116375790140,13cyclictest0-21swapper/209:25:092
116375790140,13cyclictest0-21swapper/209:25:092
116375790140,13cyclictest0-21swapper/209:20:552
116375790140,13cyclictest0-21swapper/209:10:172
116375790140,13cyclictest0-21swapper/208:58:172
116375790140,13cyclictest0-21swapper/208:32:222
116375790140,13cyclictest0-21swapper/208:26:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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