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2021-10-16 - 14:38

Intel(R) Core(TM) i5-8365UE CPU @ 1.60GHz, Linux 5.9.1-rt18 (Profile)

Latency plot of system in rack #e, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -p90 -i200 -h400 -a2-3 -t2 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackeslot1.osadl.org (updated Fri Oct 15, 2021 12:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2207490160,15cyclictest0-21swapper/311:00:013
2207490160,15cyclictest0-21swapper/310:20:143
22074901513,1cyclictest0-21swapper/309:45:153
2207490150,15cyclictest0-21swapper/312:38:503
2207490150,15cyclictest0-21swapper/312:21:283
2207490150,15cyclictest0-21swapper/312:11:243
2207490150,15cyclictest0-21swapper/311:48:583
2207490150,15cyclictest0-21swapper/311:17:573
2207490150,15cyclictest0-21swapper/311:09:523
2207490150,15cyclictest0-21swapper/310:00:253
2207490150,15cyclictest0-21swapper/309:34:463
2207490150,15cyclictest0-21swapper/309:04:263
2207490150,15cyclictest0-21swapper/308:42:173
2207490150,15cyclictest0-21swapper/308:32:073
2207490150,15cyclictest0-21swapper/307:25:493
2207490150,0cyclictest0-21swapper/308:16:363
22073901513,1cyclictest0-21swapper/210:20:002
22073901513,1cyclictest0-21swapper/208:35:002
2207390150,1cyclictest0-21swapper/212:15:132
2207390150,1cyclictest0-21swapper/211:35:002
2207390150,15cyclictest0-21swapper/212:05:072
2207390150,15cyclictest0-21swapper/210:10:522
2207390150,15cyclictest0-21swapper/209:39:282
2207390150,14cyclictest0-21swapper/208:57:272
22074901414,0cyclictest0-21swapper/311:26:163
22074901414,0cyclictest0-21swapper/311:11:533
22074901414,0cyclictest0-21swapper/311:00:363
22074901414,0cyclictest0-21swapper/310:45:043
22074901414,0cyclictest0-21swapper/309:05:093
22074901414,0cyclictest0-21swapper/308:21:383
22074901414,0cyclictest0-21swapper/308:05:303
22074901414,0cyclictest0-21swapper/307:45:363
22074901414,0cyclictest0-21swapper/307:32:303
22074901414,0cyclictest0-21swapper/307:11:293
22074901412,1cyclictest0-21swapper/312:00:243
2207490140,14cyclictest0-21swapper/312:30:373
2207490140,14cyclictest0-21swapper/312:26:363
2207490140,14cyclictest0-21swapper/312:16:413
2207490140,14cyclictest0-21swapper/312:07:133
2207490140,14cyclictest0-21swapper/311:58:173
2207490140,14cyclictest0-21swapper/311:51:533
2207490140,14cyclictest0-21swapper/311:40:303
2207490140,14cyclictest0-21swapper/311:31:423
2207490140,14cyclictest0-21swapper/311:21:103
2207490140,14cyclictest0-21swapper/310:50:093
2207490140,14cyclictest0-21swapper/310:40:393
2207490140,14cyclictest0-21swapper/310:37:073
2207490140,14cyclictest0-21swapper/310:32:013
2207490140,14cyclictest0-21swapper/310:26:413
2207490140,14cyclictest0-21swapper/310:16:483
2207490140,14cyclictest0-21swapper/310:05:313
2207490140,14cyclictest0-21swapper/309:57:103
2207490140,14cyclictest0-21swapper/309:40:363
2207490140,14cyclictest0-21swapper/309:35:243
2207490140,14cyclictest0-21swapper/309:25:583
2207490140,14cyclictest0-21swapper/309:22:083
2207490140,14cyclictest0-21swapper/309:15:383
2207490140,14cyclictest0-21swapper/309:11:013
2207490140,14cyclictest0-21swapper/308:55:013
2207490140,14cyclictest0-21swapper/308:53:563
2207490140,14cyclictest0-21swapper/308:45:043
2207490140,14cyclictest0-21swapper/308:35:043
2207490140,14cyclictest0-21swapper/308:25:133
2207490140,14cyclictest0-21swapper/308:10:023
2207490140,14cyclictest0-21swapper/308:00:533
2207490140,14cyclictest0-21swapper/307:55:433
2207490140,14cyclictest0-21swapper/307:51:483
2207490140,14cyclictest0-21swapper/307:42:213
2207490140,14cyclictest0-21swapper/307:36:103
2207490140,14cyclictest0-21swapper/307:21:513
2207490140,14cyclictest0-21swapper/307:16:153
2207490140,0cyclictest0-21swapper/311:35:533
2207490140,0cyclictest0-21swapper/310:10:273
2207490140,0cyclictest0-21swapper/309:50:223
22073901414,0cyclictest0-21swapper/210:37:212
22073901414,0cyclictest0-21swapper/209:24:482
22073901414,0cyclictest0-21swapper/208:40:412
2207390140,14cyclictest0-21swapper/212:35:032
2207390140,14cyclictest0-21swapper/212:25:052
2207390140,14cyclictest0-21swapper/212:12:052
2207390140,14cyclictest0-21swapper/212:00:312
2207390140,14cyclictest0-21swapper/211:55:432
2207390140,14cyclictest0-21swapper/211:50:552
2207390140,14cyclictest0-21swapper/211:45:032
2207390140,14cyclictest0-21swapper/211:40:062
2207390140,14cyclictest0-21swapper/211:36:442
2207390140,14cyclictest0-21swapper/211:28:322
2207390140,14cyclictest0-21swapper/211:20:212
2207390140,14cyclictest0-21swapper/211:17:332
2207390140,14cyclictest0-21swapper/211:10:252
2207390140,14cyclictest0-21swapper/211:05:402
2207390140,14cyclictest0-21swapper/211:00:222
2207390140,14cyclictest0-21swapper/210:50:222
2207390140,14cyclictest0-21swapper/210:41:302
2207390140,14cyclictest0-21swapper/210:32:142
2207390140,14cyclictest0-21swapper/210:25:052
2207390140,14cyclictest0-21swapper/210:20:162
2207390140,14cyclictest0-21swapper/210:05:532
2207390140,14cyclictest0-21swapper/210:02:122
2207390140,14cyclictest0-21swapper/209:55:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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