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2021-04-11 - 11:38

Intel(R) Core(TM) i5-8365UE CPU @ 1.60GHz, Linux 5.9.1-rt18 (Profile)

Latency plot of system in rack #e, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -p90 -i200 -h400 -a2-3 -t2 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rackeslot1.osadl.org (updated Sun Apr 11, 2021 00:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2333190236,4cyclictest0-21swapper/219:26:292
2333190226,3cyclictest0-21swapper/200:24:402
2333190221,3cyclictest0-21swapper/220:35:252
2333190215,3cyclictest0-21swapper/200:01:442
2333190181,4cyclictest0-21swapper/223:15:512
2333290170,2cyclictest0-21swapper/323:50:003
2333190170,16cyclictest0-21swapper/223:29:472
2333190170,16cyclictest0-21swapper/223:20:592
2333190170,16cyclictest0-21swapper/219:30:532
2333190170,14cyclictest0-21swapper/222:57:442
2333190160,3cyclictest0-21swapper/222:52:552
2333190160,3cyclictest0-21swapper/221:55:422
2333190160,3cyclictest0-21swapper/221:32:392
2333190160,3cyclictest0-21swapper/220:58:212
2333190160,3cyclictest0-21swapper/219:49:252
2333190160,3cyclictest0-21swapper/200:13:132
2333190160,16cyclictest0-21swapper/222:20:082
2333190160,14cyclictest0-21swapper/223:50:322
2333190160,14cyclictest0-21swapper/223:36:552
2333190160,14cyclictest0-21swapper/222:45:452
2333190160,14cyclictest0-21swapper/222:40:582
2333190160,14cyclictest0-21swapper/221:01:222
2333190160,14cyclictest0-21swapper/220:11:362
2333190160,13cyclictest0-21swapper/222:30:052
2333190160,0cyclictest0-21swapper/220:08:212
2333190160,0cyclictest0-21swapper/220:00:032
2333190160,0cyclictest0-21swapper/219:41:462
23332901515,0cyclictest0-21swapper/322:05:123
2333290150,15cyclictest0-21swapper/323:26:303
2333290150,15cyclictest0-21swapper/323:07:563
2333290150,15cyclictest0-21swapper/323:01:503
2333290150,15cyclictest0-21swapper/321:27:213
2333290150,15cyclictest0-21swapper/321:13:233
2333290150,15cyclictest0-21swapper/320:57:443
2333290150,15cyclictest0-21swapper/320:26:453
2333290150,15cyclictest0-21swapper/320:22:393
2333290150,15cyclictest0-21swapper/320:13:113
2333290150,15cyclictest0-21swapper/320:06:043
2333290150,15cyclictest0-21swapper/320:03:483
2333290150,15cyclictest0-21swapper/319:30:183
2333290150,15cyclictest0-21swapper/300:32:313
2333290150,14cyclictest0-21swapper/322:20:123
2333290150,14cyclictest0-21swapper/320:50:063
2333290150,0cyclictest0-21swapper/322:49:013
2333290150,0cyclictest0-21swapper/321:55:573
2333290150,0cyclictest0-21swapper/319:47:433
2333290150,0cyclictest0-21swapper/300:19:273
23331901515,0cyclictest0-21swapper/221:29:032
23331901513,2cyclictest0-21swapper/223:00:102
23331901513,2cyclictest0-21swapper/200:07:162
23331901512,3cyclictest0-21swapper/221:18:182
2333190150,2cyclictest0-21swapper/200:36:092
2333190150,15cyclictest0-21swapper/223:41:442
2333190150,15cyclictest0-21swapper/223:32:102
2333190150,15cyclictest0-21swapper/223:14:342
2333190150,15cyclictest0-21swapper/223:06:342
2333190150,15cyclictest0-21swapper/222:25:382
2333190150,15cyclictest0-21swapper/221:50:252
2333190150,15cyclictest0-21swapper/221:39:012
2333190150,15cyclictest0-21swapper/221:20:432
2333190150,15cyclictest0-21swapper/220:44:202
2333190150,15cyclictest0-21swapper/220:26:192
2333190150,15cyclictest0-21swapper/220:20:362
2333190150,15cyclictest0-21swapper/219:55:082
2333190150,15cyclictest0-21swapper/219:15:412
2333190150,15cyclictest0-21swapper/200:15:232
2333190150,13cyclictest0-21swapper/223:55:212
2333190150,13cyclictest0-21swapper/220:50:502
2333190150,13cyclictest0-21swapper/219:37:362
2333190150,12cyclictest0-21swapper/221:44:062
2333190150,12cyclictest0-21swapper/220:46:542
2333190150,0cyclictest0-21swapper/223:45:462
2333190150,0cyclictest0-21swapper/222:39:212
2333190150,0cyclictest0-21swapper/222:16:062
2333190150,0cyclictest0-21swapper/222:11:162
2333190150,0cyclictest0-21swapper/222:08:512
2333190150,0cyclictest0-21swapper/222:03:142
2333190150,0cyclictest0-21swapper/221:11:512
2333190150,0cyclictest0-21swapper/221:05:242
2333190150,0cyclictest0-21swapper/220:31:162
2333190150,0cyclictest0-21swapper/220:15:442
2333190150,0cyclictest0-21swapper/219:10:522
23332901414,0cyclictest0-21swapper/323:50:373
23332901414,0cyclictest0-21swapper/322:50:163
23332901414,0cyclictest0-21swapper/322:37:413
23332901414,0cyclictest0-21swapper/322:10:043
23332901414,0cyclictest0-21swapper/321:40:313
23332901414,0cyclictest0-21swapper/320:17:063
23332901414,0cyclictest0-21swapper/319:50:203
23332901414,0cyclictest0-21swapper/319:21:103
23332901413,1cyclictest0-21swapper/319:10:043
2333290140,14cyclictest0-21swapper/323:40:413
2333290140,14cyclictest0-21swapper/323:30:213
2333290140,14cyclictest0-21swapper/323:21:213
2333290140,14cyclictest0-21swapper/323:15:563
2333290140,14cyclictest0-21swapper/323:10:093
2333290140,14cyclictest0-21swapper/322:55:243
2333290140,14cyclictest0-21swapper/322:42:103
2333290140,14cyclictest0-21swapper/322:30:293
2333290140,14cyclictest0-21swapper/322:25:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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