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2022-10-02 - 01:41

x86 Intel Core i5-8365UE @1600 MHz, Linux 5.19.0-rc7-rt7 (Profile)

Latency plot of system in rack #e, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp90 -i200 -h400 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rackeslot1.osadl.org (updated Sat Oct 01, 2022 12:43:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1466665901816,1cyclictest1908668-21cut12:05:200
146666590170,16cyclictest1956109-21apt-config12:35:010
1466665901614,2cyclictest1998-21snmpd11:10:480
1466665901614,1cyclictest1934144-21tr12:20:230
146666590160,2cyclictest1795764-21kthreadcore11:00:220
146666590160,15cyclictest1600884-21cat09:05:170
146666590160,15cyclictest1568929-21kthreadcore08:35:200
146666590160,15cyclictest1520082-21sed07:55:190
146667290150,1cyclictest0-21swapper/310:56:533
146667290150,1cyclictest0-21swapper/310:56:533
146667290150,14cyclictest0-21swapper/308:30:343
146667290150,14cyclictest0-21swapper/308:25:163
1466671901513,1cyclictest0-21swapper/207:57:182
146667190150,14cyclictest0-21swapper/212:37:122
146667190150,14cyclictest0-21swapper/210:41:082
146667190150,14cyclictest0-21swapper/209:49:552
146667190150,14cyclictest0-21swapper/208:35:442
146667190150,14cyclictest0-21swapper/208:32:322
146667190150,14cyclictest0-21swapper/207:52:542
1466670901513,1cyclictest1929213-21chrt12:18:461
1466670901512,2cyclictest0-21swapper/110:52:471
146667090150,14cyclictest14717512chrt07:11:131
146667090150,14cyclictest0-21swapper/112:01:301
146667090150,14cyclictest0-21swapper/111:40:451
1466665901515,0cyclictest0-21swapper/008:00:020
1466665901513,2cyclictest1900900-21mailstats12:00:260
1466665901513,2cyclictest1755950-21grep10:35:260
146666590150,1cyclictest1732414-21ssh10:23:050
146666590150,1cyclictest1593555-21users08:55:260
146666590150,15cyclictest1858843-21chrt11:35:530
146666590150,15cyclictest1828563-21head11:20:180
146666590150,14cyclictest1998-21snmpd10:19:050
1466672901414,0cyclictest0-21swapper/312:31:513
1466672901414,0cyclictest0-21swapper/312:05:573
1466672901414,0cyclictest0-21swapper/309:48:433
1466672901414,0cyclictest0-21swapper/307:59:453
1466672901413,1cyclictest18922562sleep311:55:263
1466672901413,1cyclictest15359562chrt08:06:353
146667290140,14cyclictest0-21swapper/312:27:003
146667290140,14cyclictest0-21swapper/309:53:533
146667290140,14cyclictest0-21swapper/309:33:453
146667290140,14cyclictest0-21swapper/309:24:133
146667290140,14cyclictest0-21swapper/308:41:193
146667290140,14cyclictest0-21swapper/308:41:193
146667290140,14cyclictest0-21swapper/307:43:283
146667290140,13cyclictest0-21swapper/312:20:173
146667290140,13cyclictest0-21swapper/311:35:253
146667290140,13cyclictest0-21swapper/311:30:433
146667290140,13cyclictest0-21swapper/311:10:303
146667290140,13cyclictest0-21swapper/310:35:573
146667290140,13cyclictest0-21swapper/310:30:273
146667290140,13cyclictest0-21swapper/309:15:083
146667290140,13cyclictest0-21swapper/308:35:543
146667290140,0cyclictest0-21swapper/312:36:163
146667290140,0cyclictest0-21swapper/311:29:003
146667290140,0cyclictest0-21swapper/311:16:193
146667290140,0cyclictest0-21swapper/310:46:583
146667290140,0cyclictest0-21swapper/309:41:463
1466671901414,0cyclictest0-21swapper/210:50:372
1466671901414,0cyclictest0-21swapper/210:20:292
146667190140,14cyclictest0-21swapper/212:27:352
146667190140,13cyclictest0-21swapper/212:30:462
146667190140,13cyclictest0-21swapper/212:20:142
146667190140,13cyclictest0-21swapper/212:15:232
146667190140,13cyclictest0-21swapper/212:05:182
146667190140,13cyclictest0-21swapper/212:00:182
146667190140,13cyclictest0-21swapper/211:55:062
146667190140,13cyclictest0-21swapper/211:49:542
146667190140,13cyclictest0-21swapper/211:39:132
146667190140,13cyclictest0-21swapper/211:27:192
146667190140,13cyclictest0-21swapper/211:20:532
146667190140,13cyclictest0-21swapper/211:15:242
146667190140,13cyclictest0-21swapper/211:12:392
146667190140,13cyclictest0-21swapper/211:05:182
146667190140,13cyclictest0-21swapper/211:02:022
146667190140,13cyclictest0-21swapper/210:55:482
146667190140,13cyclictest0-21swapper/210:55:482
146667190140,13cyclictest0-21swapper/210:45:142
146667190140,13cyclictest0-21swapper/210:37:542
146667190140,13cyclictest0-21swapper/210:31:022
146667190140,13cyclictest0-21swapper/210:06:102
146667190140,13cyclictest0-21swapper/210:03:262
146667190140,13cyclictest0-21swapper/209:55:322
146667190140,13cyclictest0-21swapper/209:35:442
146667190140,13cyclictest0-21swapper/209:31:012
146667190140,13cyclictest0-21swapper/209:25:422
146667190140,13cyclictest0-21swapper/209:15:272
146667190140,13cyclictest0-21swapper/209:11:202
146667190140,13cyclictest0-21swapper/209:06:302
146667190140,13cyclictest0-21swapper/208:28:002
146667190140,13cyclictest0-21swapper/208:22:222
146667190140,13cyclictest0-21swapper/208:00:212
146667190140,13cyclictest0-21swapper/207:45:362
146667190140,13cyclictest0-21swapper/207:42:242
146667190140,13cyclictest0-21swapper/207:25:192
146667190140,13cyclictest0-21swapper/207:23:032
146667190140,13cyclictest0-21swapper/207:16:032
146667190140,0cyclictest0-21swapper/212:11:072
1466670901413,1cyclictest0-21swapper/111:07:081
1466670901412,1cyclictest0-21swapper/107:46:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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