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2022-06-27 - 17:03

x86 Intel Core i3-8145UE @2200 MHz, Linux 5.4.115-rt57 (Profile)

Latency plot of system in rack #e, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -p90 -i200 -h400 -a2-3 -t2 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot1.osadl.org (updated Wed Jan 19, 2022 12:52:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22187902414,9cyclictest0-21swapper/309:03:513
22186902312,10cyclictest0-21swapper/210:01:532
2218790181,16cyclictest0-21swapper/311:55:033
2218690181,16cyclictest0-21swapper/207:55:022
22186901715,2cyclictest0-21swapper/210:45:022
22187901615,1cyclictest0-21swapper/307:55:023
2218690162,13cyclictest0-21swapper/208:17:262
2218690162,13cyclictest0-21swapper/207:31:012
2218790158,5cyclictest0-21swapper/310:13:193
2218790137,5cyclictest0-21swapper/311:15:203
2218790136,5cyclictest0-21swapper/311:00:493
2218690131,10cyclictest0-21swapper/210:40:192
2218790129,2cyclictest0-21swapper/312:07:053
2218790129,2cyclictest0-21swapper/310:40:163
2218790129,2cyclictest0-21swapper/310:00:363
2218790129,2cyclictest0-21swapper/309:53:323
2218790129,2cyclictest0-21swapper/309:30:373
2218790129,2cyclictest0-21swapper/309:12:503
2218790129,2cyclictest0-21swapper/308:50:013
2218790129,2cyclictest0-21swapper/307:32:323
2218790129,2cyclictest0-21swapper/307:13:523
2218790127,4cyclictest0-21swapper/311:51:013
2218790127,4cyclictest0-21swapper/309:37:493
2218790126,4cyclictest0-21swapper/310:30:513
2218790126,4cyclictest0-21swapper/309:21:503
2218790122,8cyclictest0-21swapper/312:35:243
2218790122,8cyclictest0-21swapper/311:25:203
2218790122,8cyclictest0-21swapper/307:40:233
2218790118,2cyclictest0-21swapper/312:22:263
2218790118,2cyclictest0-21swapper/312:18:063
2218790118,2cyclictest0-21swapper/312:12:303
2218790118,2cyclictest0-21swapper/312:02:283
2218790118,2cyclictest0-21swapper/311:46:323
2218790118,2cyclictest0-21swapper/311:44:373
2218790118,2cyclictest0-21swapper/311:11:433
2218790118,2cyclictest0-21swapper/311:06:113
2218790118,2cyclictest0-21swapper/310:59:593
2218790118,2cyclictest0-21swapper/310:50:223
2218790118,2cyclictest0-21swapper/310:45:213
2218790118,2cyclictest0-21swapper/310:35:223
2218790118,2cyclictest0-21swapper/309:42:313
2218790118,2cyclictest0-21swapper/309:15:223
2218790118,2cyclictest0-21swapper/308:40:203
2218790118,2cyclictest0-21swapper/308:17:383
2218790118,2cyclictest0-21swapper/307:25:193
2218790118,2cyclictest0-21swapper/307:15:243
2218790117,3cyclictest0-21swapper/312:25:203
2218790117,3cyclictest0-21swapper/309:05:223
2218790117,3cyclictest0-21swapper/308:35:193
2218790117,3cyclictest0-21swapper/308:04:423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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