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2021-08-04 - 22:11

Intel(R) Core(TM) i5-8365UE CPU @ 1.60GHz, Linux 5.9.1-rt18 (Profile)

Latency plot of system in rack #e, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -p90 -i200 -h400 -a2-3 -t2 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the alll highest latencies:
System rackeslot1.osadl.org (updated Wed Aug 04, 2021 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19014901614,1cyclictest0-21swapper/210:28:242
19015901515,0cyclictest0-21swapper/311:42:143
19015901515,0cyclictest0-21swapper/310:14:383
19015901515,0cyclictest0-21swapper/310:02:043
19015901513,1cyclictest0-21swapper/308:15:223
1901590150,15cyclictest0-21swapper/312:22:553
1901590150,15cyclictest0-21swapper/312:12:313
1901590150,15cyclictest0-21swapper/312:05:273
1901590150,15cyclictest0-21swapper/311:50:543
1901590150,15cyclictest0-21swapper/311:21:123
1901590150,15cyclictest0-21swapper/311:15:253
1901590150,15cyclictest0-21swapper/311:07:083
1901590150,15cyclictest0-21swapper/309:52:003
1901590150,15cyclictest0-21swapper/309:48:143
1901590150,15cyclictest0-21swapper/309:44:093
1901590150,15cyclictest0-21swapper/309:33:293
1901590150,15cyclictest0-21swapper/309:25:383
1901590150,15cyclictest0-21swapper/308:43:243
1901590150,15cyclictest0-21swapper/308:36:223
1901590150,15cyclictest0-21swapper/308:00:363
1901590150,15cyclictest0-21swapper/307:47:303
1901590150,15cyclictest0-21swapper/307:32:053
1901590150,15cyclictest0-21swapper/307:17:253
1901590150,0cyclictest0-21swapper/310:33:143
19014901513,1cyclictest0-21swapper/207:35:172
1901490150,1cyclictest0-21swapper/212:28:072
1901490150,1cyclictest0-21swapper/211:27:452
1901490150,15cyclictest0-21swapper/207:44:032
1901490150,14cyclictest0-21swapper/210:55:282
19015901414,0cyclictest0-21swapper/312:25:003
19015901414,0cyclictest0-21swapper/311:45:293
19015901414,0cyclictest0-21swapper/311:01:143
19015901414,0cyclictest0-21swapper/309:16:303
19015901414,0cyclictest0-21swapper/309:05:043
19015901414,0cyclictest0-21swapper/309:01:303
19015901414,0cyclictest0-21swapper/308:06:423
19015901414,0cyclictest0-21swapper/307:55:373
19015901414,0cyclictest0-21swapper/307:10:513
1901590140,14cyclictest0-21swapper/312:35:083
1901590140,14cyclictest0-21swapper/312:15:053
1901590140,14cyclictest0-21swapper/312:00:193
1901590140,14cyclictest0-21swapper/311:35:023
1901590140,14cyclictest0-21swapper/311:31:403
1901590140,14cyclictest0-21swapper/311:25:063
1901590140,14cyclictest0-21swapper/310:50:453
1901590140,14cyclictest0-21swapper/310:46:293
1901590140,14cyclictest0-21swapper/310:40:523
1901590140,14cyclictest0-21swapper/310:25:283
1901590140,14cyclictest0-21swapper/310:20:403
1901590140,14cyclictest0-21swapper/310:17:023
1901590140,14cyclictest0-21swapper/310:08:033
1901590140,14cyclictest0-21swapper/309:35:143
1901590140,14cyclictest0-21swapper/309:20:413
1901590140,14cyclictest0-21swapper/309:12:193
1901590140,14cyclictest0-21swapper/308:57:023
1901590140,14cyclictest0-21swapper/308:50:583
1901590140,14cyclictest0-21swapper/308:45:463
1901590140,14cyclictest0-21swapper/308:30:433
1901590140,14cyclictest0-21swapper/308:25:343
1901590140,14cyclictest0-21swapper/308:10:403
1901590140,14cyclictest0-21swapper/307:51:223
1901590140,14cyclictest0-21swapper/307:40:133
1901590140,14cyclictest0-21swapper/307:37:163
1901590140,14cyclictest0-21swapper/307:26:223
1901590140,14cyclictest0-21swapper/307:20:233
1901590140,0cyclictest0-21swapper/312:30:433
1901590140,0cyclictest0-21swapper/311:55:033
1901590140,0cyclictest0-21swapper/311:10:563
1901590140,0cyclictest0-21swapper/310:55:413
1901590140,0cyclictest0-21swapper/310:35:083
1901590140,0cyclictest0-21swapper/309:58:063
1901590140,0cyclictest0-21swapper/308:21:303
19014901414,0cyclictest0-21swapper/210:11:072
19014901414,0cyclictest0-21swapper/208:30:002
1901490140,14cyclictest0-21swapper/212:39:222
1901490140,14cyclictest0-21swapper/212:30:492
1901490140,14cyclictest0-21swapper/212:20:182
1901490140,14cyclictest0-21swapper/212:15:102
1901490140,14cyclictest0-21swapper/212:11:592
1901490140,14cyclictest0-21swapper/212:07:092
1901490140,14cyclictest0-21swapper/211:50:012
1901490140,14cyclictest0-21swapper/211:40:242
1901490140,14cyclictest0-21swapper/211:36:162
1901490140,14cyclictest0-21swapper/211:20:502
1901490140,14cyclictest0-21swapper/211:15:012
1901490140,14cyclictest0-21swapper/211:10:432
1901490140,14cyclictest0-21swapper/211:00:252
1901490140,14cyclictest0-21swapper/210:50:012
1901490140,14cyclictest0-21swapper/210:45:062
1901490140,14cyclictest0-21swapper/210:42:242
1901490140,14cyclictest0-21swapper/210:37:452
1901490140,14cyclictest0-21swapper/210:30:372
1901490140,14cyclictest0-21swapper/210:21:342
1901490140,14cyclictest0-21swapper/210:15:342
1901490140,14cyclictest0-21swapper/210:05:442
1901490140,14cyclictest0-21swapper/209:51:352
1901490140,14cyclictest0-21swapper/209:47:242
1901490140,14cyclictest0-21swapper/209:41:352
1901490140,14cyclictest0-21swapper/209:36:322
1901490140,14cyclictest0-21swapper/209:30:342
1901490140,14cyclictest0-21swapper/209:25:342
1901490140,14cyclictest0-21swapper/209:20:172
1901490140,14cyclictest0-21swapper/209:17:402
1901490140,14cyclictest0-21swapper/209:10:222
1901490140,14cyclictest0-21swapper/209:05:072
1901490140,14cyclictest0-21swapper/209:01:542
1901490140,14cyclictest0-21swapper/208:57:142
1901490140,14cyclictest0-21swapper/208:50:052
1901490140,14cyclictest0-21swapper/208:45:242
1901490140,14cyclictest0-21swapper/208:36:352
1901490140,14cyclictest0-21swapper/208:26:152
1901490140,14cyclictest0-21swapper/208:23:192
1901490140,14cyclictest0-21swapper/208:15:382
1901490140,14cyclictest0-21swapper/208:12:192
1901490140,14cyclictest0-21swapper/208:05:592
1901490140,14cyclictest0-21swapper/207:55:122
1901490140,14cyclictest0-21swapper/207:45:362
1901490140,14cyclictest0-21swapper/207:25:302
1901490140,14cyclictest0-21swapper/207:22:462
1901490140,14cyclictest0-21swapper/207:15:182
1901490140,14cyclictest0-21swapper/207:10:282
1901490140,0cyclictest0-21swapper/212:02:092
1901490140,0cyclictest0-21swapper/211:55:292
1901490140,0cyclictest0-21swapper/211:30:012
1901490140,0cyclictest0-21swapper/211:05:482
1901490140,0cyclictest0-21swapper/210:00:062
1901490140,0cyclictest0-21swapper/209:55:322
1901490140,0cyclictest0-21swapper/208:44:372
1901490140,0cyclictest0-21swapper/208:00:122
1901490140,0cyclictest0-21swapper/207:51:492
1901490140,0cyclictest0-21swapper/207:30:232
1901490130,13cyclictest0-21swapper/211:45:032
190159020,1cyclictest0-21swapper/307:10:003
190149020,1cyclictest0-21swapper/207:10:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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