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2026-05-11 - 17:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Mon May 11, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
370644399330,4cyclictest3710156-21kthreadcore07:10:210
370644399302,23cyclictest0-21swapper/007:35:370
3706443992910,10cyclictest0-21swapper/009:20:000
3706443992817,10cyclictest0-21swapper/011:00:120
3706443992517,6cyclictest3851875-21systemd-journal11:44:550
3706443992510,9cyclictest0-21swapper/012:05:270
3706443992418,5cyclictest4073523-21wc11:30:000
3706443992418,5cyclictest3966473-21dump-pmu-power10:20:000
3706443992417,5cyclictest3890166-21latency_hist09:30:000
3706445992320,1cyclictest0-21swapper/212:30:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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