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2025-02-19 - 00:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Tue Feb 18, 2025 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4051225992623,1cyclictest0-21swapper/211:40:002
25010912617,2phc2sys0-21swapper/311:19:433
4051224992523,1cyclictest26896-21perf09:25:011
25010912518,2phc2sys0-21swapper/312:01:033
25010912518,2phc2sys0-21swapper/309:33:503
25010912418,3phc2sys0-21swapper/310:26:313
25010912418,3phc2sys0-21swapper/310:15:413
25010912418,2phc2sys0-21swapper/312:33:253
25010912418,2phc2sys0-21swapper/312:24:033
25010912418,2phc2sys0-21swapper/312:14:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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