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2024-06-22 - 05:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Fri Jun 21, 2024 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
88058121400,2sleep30-21swapper/312:25:223
45284221010,2sleep20-21swapper/207:30:022
2358491260,5ptp4l164790irq/127-enp1s0-TxRx-009:57:523
2358491250,5ptp4l164790irq/127-enp1s0-TxRx-010:14:043
2358491250,5ptp4l164790irq/127-enp1s0-TxRx-009:46:063
2358491250,4ptp4l164790irq/127-enp1s0-TxRx-009:40:493
2358491250,1ptp4l0-21swapper/310:54:123
427460992417,2cyclictest889789-21kthreadcore12:30:220
427460992417,2cyclictest1509-21in:imuxsock12:10:000
2358491240,5ptp4l164790irq/127-enp1s0-TxRx-011:41:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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