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2024-03-01 - 02:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Thu Feb 29, 2024 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33191182870,2sleep30-21swapper/321:55:253
31797202700,2sleep30-21swapper/320:10:243
356006222319,2sleep20-21swapper/200:25:422
351333722319,2sleep20-21swapper/223:57:142
349865522319,2sleep20-21swapper/223:49:162
347421622319,2sleep20-21swapper/223:32:342
346594722319,2sleep20-21swapper/223:26:452
344997422319,2sleep20-21swapper/223:16:552
343403122319,2sleep20-21swapper/223:06:292
339445622319,2sleep20-21swapper/222:41:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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