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2024-07-27 - 08:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Sat Jul 27, 2024 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
265502221050,2sleep30-21swapper/322:06:393
26816442500,3sleep11394-21dbus-daemon22:25:011
25879652300,2sleep20-21swapper/221:25:502
2354291280,2ptp4l175990irq/127-enp1s0-TxRx-022:41:033
2354291270,5ptp4l175990irq/127-enp1s0-TxRx-022:37:463
2354291270,4ptp4l175990irq/127-enp1s0-TxRx-020:10:143
2354291260,5ptp4l175990irq/127-enp1s0-TxRx-023:52:013
2354291260,4ptp4l175990irq/127-enp1s0-TxRx-023:28:293
2354291260,2ptp4l0-21swapper/323:01:433
2354291260,1ptp4l0-21swapper/322:02:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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