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2025-12-16 - 19:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Tue Dec 16, 2025 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205878421490,1sleep02058788-21kthreadcore12:08:400
173096821110,1sleep10-21swapper/107:38:401
16967542940,2sleep1341rcuc/107:13:351
169605199235,8cyclictest1-21systemd11:35:010
1696051992217,4cyclictest1326-21systemd-logind12:00:000
1696053992119,1cyclictest0-21swapper/208:30:012
169605199216,7cyclictest2005815-21awk11:25:000
1696051992116,4cyclictest1867062-21/usr/sbin/munin09:30:010
169605199206,3cyclictest0-21swapper/010:50:020
1696051992015,4cyclictest1994549-21cpuspeed11:18:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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