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2021-10-27 - 00:12

Intel(R) Core(TM) i5-8365UE CPU @ 1.60GHz, Linux 5.9.1-rt18 (Profile)

Latency plot of system in rack #e, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -p90 -i200 -h400 -a2-3 -t2 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackeslot2.osadl.org (updated Tue Jul 27, 2021 12:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26262901614,1cyclictest0-21swapper/311:55:013
2626290160,15cyclictest0-21swapper/311:02:023
2626290160,15cyclictest0-21swapper/310:11:573
2626290150,1cyclictest0-21swapper/310:27:013
2626290150,15cyclictest0-21swapper/312:12:173
2626290150,15cyclictest0-21swapper/309:34:093
2626290150,14cyclictest0-21swapper/311:40:013
26260901514,1cyclictest0-21swapper/207:11:532
26262901414,0cyclictest0-21swapper/309:22:323
26262901414,0cyclictest0-21swapper/307:15:193
26262901412,1cyclictest0-21swapper/307:57:013
2626290140,14cyclictest0-21swapper/312:39:013
2626290140,14cyclictest0-21swapper/312:30:473
2626290140,14cyclictest0-21swapper/312:15:303
2626290140,14cyclictest0-21swapper/312:15:303
2626290140,14cyclictest0-21swapper/312:06:523
2626290140,14cyclictest0-21swapper/312:00:403
2626290140,14cyclictest0-21swapper/311:55:303
2626290140,14cyclictest0-21swapper/311:46:163
2626290140,14cyclictest0-21swapper/311:40:153
2626290140,14cyclictest0-21swapper/311:34:223
2626290140,14cyclictest0-21swapper/311:19:533
2626290140,14cyclictest0-21swapper/311:10:493
2626290140,14cyclictest0-21swapper/311:05:193
2626290140,14cyclictest0-21swapper/310:56:313
2626290140,14cyclictest0-21swapper/310:41:343
2626290140,14cyclictest0-21swapper/310:30:013
2626290140,14cyclictest0-21swapper/310:23:413
2626290140,14cyclictest0-21swapper/310:18:033
2626290140,14cyclictest0-21swapper/309:56:583
2626290140,14cyclictest0-21swapper/309:51:083
2626290140,14cyclictest0-21swapper/309:42:103
2626290140,14cyclictest0-21swapper/309:37:113
2626290140,14cyclictest0-21swapper/309:27:523
2626290140,14cyclictest0-21swapper/309:01:183
2626290140,14cyclictest0-21swapper/308:50:023
2626290140,14cyclictest0-21swapper/308:41:113
2626290140,14cyclictest0-21swapper/308:26:203
2626290140,14cyclictest0-21swapper/308:17:313
2626290140,14cyclictest0-21swapper/308:12:003
2626290140,14cyclictest0-21swapper/307:53:293
2626290140,14cyclictest0-21swapper/307:41:543
2626290140,14cyclictest0-21swapper/307:39:263
2626290140,14cyclictest0-21swapper/307:30:363
2626290140,14cyclictest0-21swapper/307:26:503
2626290140,14cyclictest0-21swapper/307:21:243
2626290140,14cyclictest0-21swapper/307:12:393
2626290140,0cyclictest0-21swapper/311:22:343
2626290140,0cyclictest0-21swapper/309:19:063
2626290140,0cyclictest0-21swapper/308:35:283
2626290140,0cyclictest0-21swapper/307:47:273
26260901414,0cyclictest0-21swapper/208:37:522
26260901412,1cyclictest0-21swapper/207:24:092
2626090140,14cyclictest0-21swapper/212:38:392
2626090140,14cyclictest0-21swapper/212:33:182
2626090140,14cyclictest0-21swapper/212:23:492
2626090140,14cyclictest0-21swapper/211:55:172
2626090140,14cyclictest0-21swapper/211:51:402
2626090140,14cyclictest0-21swapper/211:48:462
2626090140,14cyclictest0-21swapper/211:36:532
2626090140,14cyclictest0-21swapper/211:34:342
2626090140,14cyclictest0-21swapper/211:19:272
2626090140,14cyclictest0-21swapper/211:11:042
2626090140,14cyclictest0-21swapper/210:47:032
2626090140,14cyclictest0-21swapper/210:35:242
2626090140,14cyclictest0-21swapper/210:20:192
2626090140,14cyclictest0-21swapper/210:15:012
2626090140,14cyclictest0-21swapper/210:02:272
2626090140,14cyclictest0-21swapper/209:54:002
2626090140,14cyclictest0-21swapper/209:30:552
2626090140,14cyclictest0-21swapper/209:15:432
2626090140,14cyclictest0-21swapper/208:40:382
2626090140,14cyclictest0-21swapper/208:34:522
2626090140,14cyclictest0-21swapper/208:22:522
2626090140,14cyclictest0-21swapper/208:13:382
2626090140,14cyclictest0-21swapper/208:07:522
2626090140,14cyclictest0-21swapper/207:44:292
2626090140,14cyclictest0-21swapper/207:35:382
2626090140,14cyclictest0-21swapper/207:32:312
2626090140,14cyclictest0-21swapper/207:27:142
2626090140,14cyclictest0-21swapper/207:18:012
2626090140,0cyclictest0-21swapper/211:08:022
2626090140,0cyclictest0-21swapper/210:11:562
2626090140,0cyclictest0-21swapper/210:05:382
2626090140,0cyclictest0-21swapper/209:56:552
2626090140,0cyclictest0-21swapper/209:09:372
2626090140,0cyclictest0-21swapper/208:25:402
2626090140,0cyclictest0-21swapper/208:16:572
26262901313,0cyclictest0-21swapper/312:27:203
26262901313,0cyclictest0-21swapper/311:25:213
26262901313,0cyclictest0-21swapper/310:50:193
26262901313,0cyclictest0-21swapper/310:36:043
26262901313,0cyclictest0-21swapper/310:06:423
26262901313,0cyclictest0-21swapper/310:02:563
26262901313,0cyclictest0-21swapper/308:31:433
26262901313,0cyclictest0-21swapper/308:20:113
26262901313,0cyclictest0-21swapper/308:05:483
2626290130,13cyclictest0-21swapper/309:10:363
2626290130,13cyclictest0-21swapper/308:56:013
2626290130,13cyclictest0-21swapper/308:56:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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