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2022-10-02 - 01:47

x86 Intel Core i5-8365UE @1600 MHz, Linux 5.19.0-rc7-rt7 (Profile)

Latency plot of system in rack #e, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp90 -i200 -h400 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rackeslot2.osadl.org (updated Sat Oct 01, 2022 12:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
140330190170,16cyclictest1755254-21kthreadcore11:19:360
1403301901613,2cyclictest1594923-21munin-run09:43:250
140330190161,1cyclictest1784670-21ssh11:38:030
140330190160,1cyclictest1810575-21munin-run11:54:360
140330190160,15cyclictest0-21swapper/009:35:310
1403313901514,1cyclictest575-21kworker/3:2+events_freezable_power_12:38:463
140331390150,14cyclictest0-21swapper/311:59:543
140331390150,14cyclictest0-21swapper/311:29:283
140331390150,14cyclictest0-21swapper/310:59:283
140331390150,14cyclictest0-21swapper/309:48:323
140331390150,14cyclictest0-21swapper/309:03:213
140331390150,14cyclictest0-21swapper/308:07:433
140330790150,14cyclictest0-21swapper/211:12:042
140330790150,14cyclictest0-21swapper/209:25:262
140330690150,14cyclictest0-21swapper/111:51:241
140330690150,14cyclictest0-21swapper/108:43:121
1403301901514,1cyclictest0-21swapper/011:05:450
1403301901513,2cyclictest1745148-21fschecks_time11:14:300
1403301901513,2cyclictest1642272-21rm10:10:020
1403301901513,1cyclictest1620613-21df_inode09:58:530
140330190150,1cyclictest1818343-21sh11:59:060
140330190150,1cyclictest1794852-21perl11:44:480
140330190150,1cyclictest1742606-21sh11:11:420
140330190150,1cyclictest1476009-21diskstats08:12:560
140330190150,15cyclictest1613168-21cat09:53:530
140330190150,15cyclictest1561046-21ssh09:22:280
140330190150,14cyclictest1786297-21expr11:39:440
140330190150,14cyclictest1526163-21perl08:58:200
140330190150,14cyclictest1431977-21hddtemp_smartct07:32:380
1403313901414,0cyclictest0-21swapper/308:58:093
1403313901414,0cyclictest0-21swapper/308:18:253
1403313901414,0cyclictest0-21swapper/307:47:153
1403313901413,1cyclictest575-21kworker/3:2+events_freezable_power_07:28:303
140331390140,14cyclictest0-21swapper/311:23:543
140331390140,14cyclictest0-21swapper/309:11:373
140331390140,14cyclictest0-21swapper/308:50:323
140331390140,14cyclictest0-21swapper/308:33:183
140331390140,14cyclictest0-21swapper/307:47:363
140331390140,14cyclictest0-21swapper/307:25:203
140331390140,14cyclictest0-21swapper/307:17:503
140331390140,14cyclictest0-21swapper/307:07:133
140331390140,13cyclictest0-21swapper/311:55:033
140331390140,13cyclictest0-21swapper/310:54:383
140331390140,13cyclictest0-21swapper/308:37:583
140331390140,0cyclictest0-21swapper/308:12:433
140331390140,0cyclictest0-21swapper/307:36:423
140330790140,14cyclictest0-21swapper/208:18:192
140330790140,14cyclictest0-21swapper/207:56:512
140330790140,13cyclictest0-21swapper/212:35:052
140330790140,13cyclictest0-21swapper/212:21:412
140330790140,13cyclictest0-21swapper/211:56:402
140330790140,13cyclictest0-21swapper/211:45:512
140330790140,13cyclictest0-21swapper/211:31:582
140330790140,13cyclictest0-21swapper/211:24:492
140330790140,13cyclictest0-21swapper/211:04:132
140330790140,13cyclictest0-21swapper/210:56:442
140330790140,13cyclictest0-21swapper/210:20:082
140330790140,13cyclictest0-21swapper/210:10:442
140330790140,13cyclictest0-21swapper/209:59:542
140330790140,13cyclictest0-21swapper/209:53:462
140330790140,13cyclictest0-21swapper/209:45:082
140330790140,13cyclictest0-21swapper/209:43:052
140330790140,13cyclictest0-21swapper/209:34:312
140330790140,13cyclictest0-21swapper/209:28:312
140330790140,13cyclictest0-21swapper/209:15:062
140330790140,13cyclictest0-21swapper/209:08:322
140330790140,13cyclictest0-21swapper/209:08:012
140330790140,13cyclictest0-21swapper/209:00:582
140330790140,13cyclictest0-21swapper/208:38:402
140330790140,13cyclictest0-21swapper/208:33:092
140330790140,0cyclictest0-21swapper/207:57:432
140330690140,13cyclictest0-21swapper/112:35:151
140330690140,13cyclictest0-21swapper/112:34:451
140330690140,13cyclictest0-21swapper/112:21:081
140330690140,13cyclictest0-21swapper/112:01:011
140330690140,13cyclictest0-21swapper/111:41:411
140330690140,13cyclictest0-21swapper/111:34:451
140330690140,13cyclictest0-21swapper/111:31:141
140330690140,13cyclictest0-21swapper/111:26:441
140330690140,13cyclictest0-21swapper/111:19:361
140330690140,13cyclictest0-21swapper/111:14:321
140330690140,13cyclictest0-21swapper/111:12:581
140330690140,13cyclictest0-21swapper/111:04:121
140330690140,13cyclictest0-21swapper/111:01:161
140330690140,13cyclictest0-21swapper/110:31:281
140330690140,13cyclictest0-21swapper/110:10:551
140330690140,13cyclictest0-21swapper/110:00:061
140330690140,13cyclictest0-21swapper/109:49:491
140330690140,13cyclictest0-21swapper/109:44:291
140330690140,13cyclictest0-21swapper/109:39:281
140330690140,13cyclictest0-21swapper/109:34:401
140330690140,13cyclictest0-21swapper/109:28:501
140330690140,13cyclictest0-21swapper/109:26:171
140330690140,13cyclictest0-21swapper/109:13:331
140330690140,13cyclictest0-21swapper/109:10:571
140330690140,13cyclictest0-21swapper/109:00:041
140330690140,13cyclictest0-21swapper/108:39:121
140330690140,13cyclictest0-21swapper/108:28:301
140330690140,13cyclictest0-21swapper/108:23:181
140330690140,13cyclictest0-21swapper/107:58:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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