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2025-02-11 - 07:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Feb 11, 2025 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31272482340,1sleep00-21swapper/021:30:170
32193612310,2sleep30-21swapper/322:29:113
34148592300,1sleep00-21swapper/000:33:250
31714022300,3sleep03171408-21kthreadcore21:55:250
2946469992817,5cyclictest0-21swapper/222:20:012
2946468992614,3cyclictest0-21swapper/122:35:011
2946468992515,3cyclictest3104315-21cut21:15:021
2946467992516,8cyclictest3222014-21kthreadcore22:30:170
25010912518,2phc2sys0-21swapper/323:24:243
25010912418,3phc2sys0-21swapper/322:38:053
25010912418,3phc2sys0-21swapper/321:48:113
25010912418,3phc2sys0-21swapper/300:25:583
25010912418,3phc2sys0-21swapper/300:05:183
25010912418,2phc2sys0-21swapper/323:57:143
25010912418,2phc2sys0-21swapper/323:48:573
25010912418,2phc2sys0-21swapper/323:48:563
25010912418,2phc2sys0-21swapper/323:35:133
25010912418,2phc2sys0-21swapper/323:33:423
25010912418,2phc2sys0-21swapper/323:17:013
25010912418,2phc2sys0-21swapper/323:13:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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