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2025-12-12 - 14:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Dec 12, 2025 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
333904522240,3sleep30-21swapper/321:30:013
316921621590,2sleep33169219-21turbostat19:20:003
33693932970,1sleep13369397-21kthreadcore21:45:101
34057222430,1sleep00-21swapper/022:05:490
3160040993129,1cyclictest0-21swapper/200:30:022
3160039993128,2cyclictest3435186-21cstates22:25:011
34509282300,1sleep13450927-21ssh22:33:311
3160039993023,2cyclictest170550irq/121-eno120:05:011
3160038992724,2cyclictest0-21swapper/021:00:010
3160040992623,1cyclictest0-21swapper/200:00:012
3160038992421,2cyclictest3574816-21grep23:45:010
3160038992416,7cyclictest3206206-21systemd-run19:50:000
3160038992414,5cyclictest0-21swapper/023:20:020
316003899230,18cyclictest3592380-21latency_hist23:55:010
3160040992219,1cyclictest0-21swapper/223:25:002
3160040992219,1cyclictest0-21swapper/221:15:012
3160038992219,2cyclictest3632624-21sh00:25:010
3160038992213,5cyclictest3584110-21sh23:50:020
3160038992211,6cyclictest0-21swapper/021:30:000
3160040992117,1cyclictest0-21swapper/200:40:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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