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2025-07-18 - 00:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 17, 2025 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
384395021130,2sleep20-21swapper/212:00:182
375144421020,2sleep30-21swapper/311:05:213
36683732970,2sleep30-21swapper/310:20:163
38872952340,2sleep30-21swapper/312:25:173
924598260,4rtkit-daemon3886629-21latency_hist12:25:011
25010912618,4phc2sys0-21swapper/309:15:233
25010912518,3phc2sys0-21swapper/311:23:143
25010912518,2phc2sys0-21swapper/311:50:283
3397487992414,5cyclictest3694110-21systemd-run10:35:020
25010912418,3phc2sys0-21swapper/312:35:353
25010912418,3phc2sys0-21swapper/312:05:303
25010912418,3phc2sys0-21swapper/311:57:283
25010912418,3phc2sys0-21swapper/311:04:303
25010912418,3phc2sys0-21swapper/307:05:273
25010912418,2phc2sys0-21swapper/312:34:283
25010912418,2phc2sys0-21swapper/312:10:443
25010912418,2phc2sys0-21swapper/310:01:423
25010912418,2phc2sys0-21swapper/309:36:373
25010912418,2phc2sys0-21swapper/309:29:433
25010912418,2phc2sys0-21swapper/308:48:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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