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2025-07-07 - 02:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Jul 06, 2025 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
284023521050,2sleep30-21swapper/312:15:263
23966502920,2sleep20-21swapper/207:35:022
25010912817,4phc2sys0-21swapper/310:41:333
25010912518,2phc2sys0-21swapper/312:25:253
25010912518,2phc2sys0-21swapper/311:58:443
25010912518,2phc2sys0-21swapper/310:25:383
25010912518,2phc2sys0-21swapper/310:10:343
25010912518,2phc2sys0-21swapper/310:10:343
25010912518,2phc2sys0-21swapper/310:08:383
25010912418,4phc2sys27994282sleep311:54:093
25010912418,3phc2sys0-21swapper/312:30:213
25010912418,3phc2sys0-21swapper/312:02:033
25010912418,3phc2sys0-21swapper/311:42:033
25010912418,3phc2sys0-21swapper/310:50:253
25010912418,3phc2sys0-21swapper/310:48:573
25010912418,2phc2sys0-21swapper/312:38:233
25010912418,2phc2sys0-21swapper/311:07:333
25010912418,2phc2sys0-21swapper/310:00:203
25010912418,2phc2sys0-21swapper/309:36:323
25010912418,2phc2sys0-21swapper/309:18:043
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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