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2021-02-26 - 22:39

Intel(R) Core(TM) i5-8365UE CPU @ 1.60GHz, Linux 5.9.1-rt18 (Profile)

Latency plot of system in rack #e, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -p90 -i200 -h400 -a2-3 -t2 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot2.osadl.org (updated Fri Feb 26, 2021 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
305990400,21cyclictest0-21swapper/310:48:533
3058901914,1cyclictest0-21swapper/210:51:142
3058901914,1cyclictest0-21swapper/208:00:012
305990160,15cyclictest0-21swapper/310:41:053
305990160,15cyclictest0-21swapper/309:10:003
305890160,15cyclictest0-21swapper/208:11:092
305990150,1cyclictest0-21swapper/310:35:013
305990150,1cyclictest0-21swapper/308:41:133
305990150,15cyclictest0-21swapper/310:16:273
305990150,15cyclictest0-21swapper/309:15:133
305990150,15cyclictest0-21swapper/307:43:553
305990150,14cyclictest0-21swapper/312:06:053
305990150,14cyclictest0-21swapper/309:14:413
3058901513,1cyclictest0-21swapper/210:05:002
305890150,1cyclictest0-21swapper/212:21:052
3059901414,0cyclictest0-21swapper/312:00:003
3059901414,0cyclictest0-21swapper/311:24:543
3059901414,0cyclictest0-21swapper/308:57:383
3059901414,0cyclictest0-21swapper/308:35:383
3059901413,1cyclictest0-21swapper/308:28:163
305990140,14cyclictest0-21swapper/312:33:383
305990140,14cyclictest0-21swapper/312:18:173
305990140,14cyclictest0-21swapper/312:10:573
305990140,14cyclictest0-21swapper/311:54:013
305990140,14cyclictest0-21swapper/311:48:223
305990140,14cyclictest0-21swapper/311:36:273
305990140,14cyclictest0-21swapper/311:15:143
305990140,14cyclictest0-21swapper/311:14:193
305990140,14cyclictest0-21swapper/311:08:483
305990140,14cyclictest0-21swapper/311:02:263
305990140,14cyclictest0-21swapper/310:56:273
305990140,14cyclictest0-21swapper/310:29:033
305990140,14cyclictest0-21swapper/310:23:143
305990140,14cyclictest0-21swapper/310:12:153
305990140,14cyclictest0-21swapper/310:05:083
305990140,14cyclictest0-21swapper/310:00:193
305990140,14cyclictest0-21swapper/309:43:153
305990140,14cyclictest0-21swapper/309:36:453
305990140,14cyclictest0-21swapper/309:25:593
305990140,14cyclictest0-21swapper/309:20:373
305990140,14cyclictest0-21swapper/309:03:533
305990140,14cyclictest0-21swapper/308:51:103
305990140,14cyclictest0-21swapper/308:22:333
305990140,14cyclictest0-21swapper/308:16:553
305990140,14cyclictest0-21swapper/308:11:473
305990140,14cyclictest0-21swapper/308:01:093
305990140,14cyclictest0-21swapper/307:37:323
305990140,14cyclictest0-21swapper/307:30:593
305990140,14cyclictest0-21swapper/307:25:373
305990140,0cyclictest0-21swapper/312:28:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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