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2022-06-29 - 15:06

x86 Intel Core i3-8145UE @2200 MHz, Linux 5.16.0-rt15 (Profile)

Latency plot of system in rack #e, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -p90 -i200 -h400 -a2-3 -t2 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot2.osadl.org (updated Wed Jan 19, 2022 12:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
561790170,14cyclictest0-21swapper/212:31:562
561790170,14cyclictest0-21swapper/210:36:522
5617901614,1cyclictest158672chrt09:22:212
561790160,14cyclictest0-21swapper/211:34:302
561790160,14cyclictest0-21swapper/209:39:582
561790160,14cyclictest0-21swapper/209:11:192
561790160,14cyclictest0-21swapper/208:42:092
561790160,14cyclictest0-21swapper/208:15:202
561790160,14cyclictest0-21swapper/208:13:552
561790160,14cyclictest0-21swapper/207:17:332
5618901512,0cyclictest0-21swapper/308:06:583
561890150,1cyclictest0-21swapper/307:50:023
561890150,15cyclictest0-21swapper/311:48:233
561890150,15cyclictest0-21swapper/311:31:543
561890150,15cyclictest0-21swapper/311:09:023
561890150,15cyclictest0-21swapper/310:46:233
561890150,15cyclictest0-21swapper/309:31:283
561890150,15cyclictest0-21swapper/309:02:293
5617901514,1cyclictest0-21swapper/210:08:082
5617901513,1cyclictest0-21swapper/208:20:362
561790150,15cyclictest0-21swapper/211:35:082
561790150,15cyclictest0-21swapper/207:45:242
561790150,13cyclictest0-21swapper/212:02:242
561790150,0cyclictest0-21swapper/211:05:102
561790150,0cyclictest0-21swapper/211:04:442
561790150,0cyclictest0-21swapper/209:40:182
5618901414,0cyclictest0-21swapper/311:02:103
5618901414,0cyclictest0-21swapper/310:50:323
5618901414,0cyclictest0-21swapper/308:56:443
5618901414,0cyclictest0-21swapper/308:45:593
5618901414,0cyclictest0-21swapper/308:23:303
5618901414,0cyclictest0-21swapper/307:19:263
5618901414,0cyclictest0-21swapper/307:14:003
561890140,14cyclictest0-21swapper/312:39:143
561890140,14cyclictest0-21swapper/312:33:083
561890140,14cyclictest0-21swapper/312:27:383
561890140,14cyclictest0-21swapper/312:27:383
561890140,14cyclictest0-21swapper/312:23:153
561890140,14cyclictest0-21swapper/312:16:533
561890140,14cyclictest0-21swapper/312:10:293
561890140,14cyclictest0-21swapper/312:05:143
561890140,14cyclictest0-21swapper/311:55:093
561890140,14cyclictest0-21swapper/311:53:433
561890140,14cyclictest0-21swapper/311:42:233
561890140,14cyclictest0-21swapper/311:36:553
561890140,14cyclictest0-21swapper/311:25:493
561890140,14cyclictest0-21swapper/311:19:353
561890140,14cyclictest0-21swapper/311:13:243
561890140,14cyclictest0-21swapper/310:56:443
561890140,14cyclictest0-21swapper/310:40:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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