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2022-07-01 - 23:06

x86 Intel Core i3-8145UE @2200 MHz, Linux 5.16.0-rt15 (Profile)

Latency plot of system in rack #e, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -p90 -i200 -h400 -a2-3 -t2 -q done
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the alll highest latencies:
System rackeslot2.osadl.org (updated Wed Jan 19, 2022 12:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
561790170,14cyclictest0-21swapper/212:31:562
561790170,14cyclictest0-21swapper/210:36:522
5617901614,1cyclictest158672chrt09:22:212
561790160,14cyclictest0-21swapper/211:34:302
561790160,14cyclictest0-21swapper/209:39:582
561790160,14cyclictest0-21swapper/209:11:192
561790160,14cyclictest0-21swapper/208:42:092
561790160,14cyclictest0-21swapper/208:15:202
561790160,14cyclictest0-21swapper/208:13:552
561790160,14cyclictest0-21swapper/207:17:332
5618901512,0cyclictest0-21swapper/308:06:583
561890150,1cyclictest0-21swapper/307:50:023
561890150,15cyclictest0-21swapper/311:48:233
561890150,15cyclictest0-21swapper/311:31:543
561890150,15cyclictest0-21swapper/311:09:023
561890150,15cyclictest0-21swapper/310:46:233
561890150,15cyclictest0-21swapper/309:31:283
561890150,15cyclictest0-21swapper/309:02:293
5617901514,1cyclictest0-21swapper/210:08:082
5617901513,1cyclictest0-21swapper/208:20:362
561790150,15cyclictest0-21swapper/211:35:082
561790150,15cyclictest0-21swapper/207:45:242
561790150,13cyclictest0-21swapper/212:02:242
561790150,0cyclictest0-21swapper/211:05:102
561790150,0cyclictest0-21swapper/211:04:442
561790150,0cyclictest0-21swapper/209:40:182
5618901414,0cyclictest0-21swapper/311:02:103
5618901414,0cyclictest0-21swapper/310:50:323
5618901414,0cyclictest0-21swapper/308:56:443
5618901414,0cyclictest0-21swapper/308:45:593
5618901414,0cyclictest0-21swapper/308:23:303
5618901414,0cyclictest0-21swapper/307:19:263
5618901414,0cyclictest0-21swapper/307:14:003
561890140,14cyclictest0-21swapper/312:39:143
561890140,14cyclictest0-21swapper/312:33:083
561890140,14cyclictest0-21swapper/312:27:383
561890140,14cyclictest0-21swapper/312:27:383
561890140,14cyclictest0-21swapper/312:23:153
561890140,14cyclictest0-21swapper/312:16:533
561890140,14cyclictest0-21swapper/312:10:293
561890140,14cyclictest0-21swapper/312:05:143
561890140,14cyclictest0-21swapper/311:55:093
561890140,14cyclictest0-21swapper/311:53:433
561890140,14cyclictest0-21swapper/311:42:233
561890140,14cyclictest0-21swapper/311:36:553
561890140,14cyclictest0-21swapper/311:25:493
561890140,14cyclictest0-21swapper/311:19:353
561890140,14cyclictest0-21swapper/311:13:243
561890140,14cyclictest0-21swapper/310:56:443
561890140,14cyclictest0-21swapper/310:40:473
561890140,14cyclictest0-21swapper/310:35:093
561890140,14cyclictest0-21swapper/310:28:073
561890140,14cyclictest0-21swapper/310:22:263
561890140,14cyclictest0-21swapper/310:17:033
561890140,14cyclictest0-21swapper/310:10:343
561890140,14cyclictest0-21swapper/310:05:553
561890140,14cyclictest0-21swapper/310:00:033
561890140,14cyclictest0-21swapper/309:55:253
561890140,14cyclictest0-21swapper/309:53:533
561890140,14cyclictest0-21swapper/309:42:453
561890140,14cyclictest0-21swapper/309:36:423
561890140,14cyclictest0-21swapper/309:20:503
561890140,14cyclictest0-21swapper/309:14:003
561890140,14cyclictest0-21swapper/309:09:093
561890140,14cyclictest0-21swapper/308:51:333
561890140,14cyclictest0-21swapper/308:51:333
561890140,14cyclictest0-21swapper/308:34:143
561890140,14cyclictest0-21swapper/308:28:173
561890140,14cyclictest0-21swapper/308:16:393
561890140,14cyclictest0-21swapper/308:12:183
561890140,14cyclictest0-21swapper/307:55:283
561890140,14cyclictest0-21swapper/307:55:283
561890140,14cyclictest0-21swapper/307:48:193
561890140,14cyclictest0-21swapper/307:42:483
561890140,14cyclictest0-21swapper/307:32:053
561890140,14cyclictest0-21swapper/307:25:283
561890140,0cyclictest0-21swapper/312:00:383
561890140,0cyclictest0-21swapper/309:48:263
561890140,0cyclictest0-21swapper/309:15:053
561890140,0cyclictest0-21swapper/308:40:433
561890140,0cyclictest0-21swapper/307:37:093
561890140,0cyclictest0-21swapper/307:20:203
5617901414,0cyclictest0-21swapper/207:40:032
561790140,14cyclictest0-21swapper/212:36:512
561790140,14cyclictest0-21swapper/212:25:252
561790140,14cyclictest0-21swapper/212:25:252
561790140,14cyclictest0-21swapper/212:20:502
561790140,14cyclictest0-21swapper/212:19:182
561790140,14cyclictest0-21swapper/211:56:332
561790140,14cyclictest0-21swapper/211:51:122
561790140,14cyclictest0-21swapper/211:45:222
561790140,14cyclictest0-21swapper/211:40:062
561790140,14cyclictest0-21swapper/211:27:482
561790140,14cyclictest0-21swapper/211:22:582
561790140,14cyclictest0-21swapper/211:16:422
561790140,14cyclictest0-21swapper/211:11:502
561790140,14cyclictest0-21swapper/210:59:152
561790140,14cyclictest0-21swapper/210:54:562
561790140,14cyclictest0-21swapper/210:42:132
561790140,14cyclictest0-21swapper/210:31:472
561790140,14cyclictest0-21swapper/210:25:172
561790140,14cyclictest0-21swapper/210:15:122
561790140,14cyclictest0-21swapper/210:14:472
561790140,14cyclictest0-21swapper/210:02:082
561790140,14cyclictest0-21swapper/209:57:342
561790140,14cyclictest0-21swapper/209:50:522
561790140,14cyclictest0-21swapper/209:28:242
561790140,14cyclictest0-21swapper/209:17:312
561790140,14cyclictest0-21swapper/209:05:242
561790140,14cyclictest0-21swapper/209:00:032
561790140,14cyclictest0-21swapper/208:53:342
561790140,14cyclictest0-21swapper/208:53:342
561790140,14cyclictest0-21swapper/208:48:082
561790140,14cyclictest0-21swapper/208:37:082
561790140,14cyclictest0-21swapper/208:30:592
561790140,14cyclictest0-21swapper/208:25:032
561790140,14cyclictest0-21swapper/207:56:542
561790140,14cyclictest0-21swapper/207:56:542
561790140,14cyclictest0-21swapper/207:50:582
561790140,14cyclictest0-21swapper/207:35:062
561790140,14cyclictest0-21swapper/207:28:382
561790140,14cyclictest0-21swapper/207:22:332
561790140,14cyclictest0-21swapper/207:12:052
561790140,0cyclictest0-21swapper/212:07:472
561790140,0cyclictest0-21swapper/210:48:002
561790140,0cyclictest0-21swapper/210:20:062
561790140,0cyclictest0-21swapper/209:45:512
561790140,0cyclictest0-21swapper/209:33:562
561790140,0cyclictest0-21swapper/208:59:072
561790140,0cyclictest0-21swapper/208:09:232
561790140,0cyclictest0-21swapper/207:34:432
5618901313,0cyclictest0-21swapper/309:25:083
561890130,13cyclictest0-21swapper/310:33:243
561890130,13cyclictest0-21swapper/308:35:033
561890130,13cyclictest0-21swapper/308:00:223
561890130,0cyclictest0-21swapper/311:20:143
561790130,13cyclictest0-21swapper/212:13:122
561790130,0cyclictest0-21swapper/208:02:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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