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2024-09-11 - 18:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Wed Sep 11, 2024 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
264075699770,75cyclictest0-21swapper/109:45:001
2640756996762,3cyclictest0-21swapper/111:05:201
264075699670,1cyclictest0-21swapper/107:50:231
264075699650,63cyclictest0-21swapper/111:45:231
2640756996446,16cyclictest2662962-21kworker/1:008:30:151
2640756996340,21cyclictest2647690-21kworker/1:307:40:141
264075699630,62cyclictest0-21swapper/109:10:131
2640756996145,15cyclictest2733042-21kworker/1:312:10:571
2640756996144,16cyclictest2718629-21kworker/1:211:15:151
2640756996144,16cyclictest2644454-21kworker/1:207:25:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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