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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8
Special All - All RT - Optimization - Ethernet - Thumbnails - Next

Click here to display the system's profile data or here to proceed to next system.

Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.
Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system

Characteristics of the 100 highest latencies:

System rackeslot3s.osadl.org (updated Tue Jul 01, 2025 12:45:03)
Delayed (victim)					Switcher (culprit)			Timestamp	CPU
PID	Prio	Total latency (µs)	T^(,W^*) latency (µs)	Cmd	PID	Prio	Cmd	Timestamp	CPU
2730399	99	72	3,6	cyclictest	13	1	rcu_preempt	10:45:01	0
2730399	99	68	33,5	cyclictest	13	1	rcu_preempt	10:20:02	0
2730399	99	65	11,6	cyclictest	13	1	rcu_preempt	09:10:02	0
2730414	99	64	14,6	cyclictest	13	1	rcu_preempt	10:05:02	3
2730414	99	63	21,7	cyclictest	37	-21	ksoftirqd/3	12:00:02	3
2730411	99	63	13,5	cyclictest	13	1	rcu_preempt	12:00:00	2
2730399	99	63	4,53	cyclictest	2738149	-21	modprobe	09:40:00	0
2730414	99	62	13,6	cyclictest	13	1	rcu_preempt	08:40:01	3
2730414	99	62	10,7	cyclictest	13	1	rcu_preempt	12:35:02	3
2730411	99	61	11,6	cyclictest	13	1	rcu_preempt	12:25:00	2
2730399	99	61	43,9	cyclictest	12	-21	ksoftirqd/0	11:30:01	0
2730399	99	61	25,32	cyclictest	2742105	-21	ls	10:55:02	0
2730399	99	61	12,6	cyclictest	13	1	rcu_preempt	08:30:01	0
2730399	99	61	10,6	cyclictest	13	1	rcu_preempt	09:20:00	0
2730399	99	61	10,6	cyclictest	13	1	rcu_preempt	08:50:02	0
2730414	99	60	10,5	cyclictest	13	1	rcu_preempt	12:15:02	3
2730414	99	60	10,5	cyclictest	13	1	rcu_preempt	12:15:02	3
2730411	99	60	26,10	cyclictest	30	-21	ksoftirqd/2	12:40:01	2
2730411	99	60	26,10	cyclictest	30	-21	ksoftirqd/2	12:40:01	2
2730399	99	60	5,8	cyclictest	12	-21	ksoftirqd/0	12:29:59	0
2730399	99	60	27,14	cyclictest	12	-21	ksoftirqd/0	07:48:25	0
2730414	99	59	7,9	cyclictest	37	-21	ksoftirqd/3	12:20:00	3
2730414	99	59	11,7	cyclictest	13	1	rcu_preempt	07:45:01	3
2730411	99	59	9,6	cyclictest	13	1	rcu_preempt	11:30:00	2
2730411	99	59	18,11	cyclictest	30	-21	ksoftirqd/2	08:40:01	2
2730411	99	59	15,5	cyclictest	13	1	rcu_preempt	11:20:01	2
2730399	99	59	3,6	cyclictest	13	1	rcu_preempt	08:19:59	0
2730399	99	59	2,5	cyclictest	13	1	rcu_preempt	11:20:01	0
2730399	99	59	1,4	cyclictest	13	1	rcu_preempt	11:37:01	0
2730414	99	58	11,6	cyclictest	13	1	rcu_preempt	11:50:01	3
2730411	99	58	8,9	cyclictest	30	-21	ksoftirqd/2	09:00:00	2
2730411	99	58	8,8	cyclictest	30	-21	ksoftirqd/2	11:25:02	2
2730411	99	58	8,5	cyclictest	13	1	rcu_preempt	08:20:02	2
2730411	99	58	8,10	cyclictest	30	-21	ksoftirqd/2	07:19:59	2
2730411	99	58	6,6	cyclictest	13	1	rcu_preempt	08:30:02	2
2730411	99	58	11,5	cyclictest	13	1	rcu_preempt	10:20:02	2
2730399	99	58	7,5	cyclictest	13	1	rcu_preempt	08:25:02	0
2730399	99	58	4,7	cyclictest	12	-21	ksoftirqd/0	10:05:00	0
2730399	99	58	16,6	cyclictest	13	1	rcu_preempt	09:44:59	0
2730399	99	58	13,7	cyclictest	13	1	rcu_preempt	07:30:02	0
2730414	99	57	6,7	cyclictest	13	1	rcu_preempt	10:20:01	3
2730414	99	57	6,5	cyclictest	13	1	rcu_preempt	10:55:01	3
2730414	99	57	5,6	cyclictest	13	1	rcu_preempt	07:40:00	3
2730414	99	57	4,8	cyclictest	37	-21	ksoftirqd/3	11:00:00	3
2730414	99	57	4,11	cyclictest	37	-21	ksoftirqd/3	09:20:02	3
2730414	99	57	13,6	cyclictest	13	1	rcu_preempt	09:00:00	3
2730414	99	57	13,5	cyclictest	13	1	rcu_preempt	07:15:01	3
2730414	99	57	10,6	cyclictest	13	1	rcu_preempt	08:20:01	3
2730411	99	57	2,6	cyclictest	30	-21	ksoftirqd/2	10:43:22	2
2730411	99	57	14,6	cyclictest	13	1	rcu_preempt	08:15:01	2
2730399	99	57	8,6	cyclictest	13	1	rcu_preempt	07:35:02	0
2730414	99	56	13,6	cyclictest	13	1	rcu_preempt	11:55:01	3
2730414	99	56	13,6	cyclictest	13	1	rcu_preempt	09:15:01	3
2730414	99	56	13,6	cyclictest	13	1	rcu_preempt	08:15:02	3
2730411	99	56	8,6	cyclictest	13	1	rcu_preempt	10:00:03	2
2730411	99	56	4,8	cyclictest	30	-21	ksoftirqd/2	12:20:01	2
2730411	99	56	12,6	cyclictest	13	1	rcu_preempt	07:10:02	2
2730411	99	56	12,5	cyclictest	13	1	rcu_preempt	10:55:02	2
2730411	99	56	10,6	cyclictest	13	1	rcu_preempt	08:00:02	2
2730407	99	56	35,9	cyclictest	23	-21	ksoftirqd/1	11:50:02	1
2730399	99	56	7,6	cyclictest	13	1	rcu_preempt	07:39:59	0
2730399	99	56	37,8	cyclictest	12	-21	ksoftirqd/0	09:04:59	0
2730399	99	56	1,9	cyclictest	12	-21	ksoftirqd/0	09:25:01	0
2730399	99	56	11,5	cyclictest	13	1	rcu_preempt	10:10:00	0
2730414	99	55	7,5	cyclictest	13	1	rcu_preempt	11:20:01	3
2730414	99	55	1,8	cyclictest	1	-21	systemd	11:35:01	3
2730414	99	55	12,6	cyclictest	13	1	rcu_preempt	08:00:02	3
2730411	99	55	9,7	cyclictest	13	1	rcu_preempt	11:45:00	2
2730411	99	55	6,5	cyclictest	13	1	rcu_preempt	08:55:03	2
2730411	99	55	6,5	cyclictest	13	1	rcu_preempt	08:55:03	2
2730411	99	55	12,6	cyclictest	13	1	rcu_preempt	09:25:00	2
2730411	99	55	11,6	cyclictest	13	1	rcu_preempt	11:40:00	2
2730411	99	55	10,6	cyclictest	13	1	rcu_preempt	12:05:01	2
2730399	99	55	15,5	cyclictest	13	1	rcu_preempt	11:45:00	0
2730399	99	55	10,5	cyclictest	13	1	rcu_preempt	08:45:02	0
2730414	99	54	9,5	cyclictest	13	1	rcu_preempt	09:25:01	3
2730414	99	54	5,9	cyclictest	13	1	rcu_preempt	07:35:02	3
2730414	99	54	5,10	cyclictest	37	-21	ksoftirqd/3	10:15:00	3
2730414	99	54	2,11	cyclictest	37	-21	ksoftirqd/3	07:25:01	3
2730414	99	54	15,7	cyclictest	13	1	rcu_preempt	09:10:01	3
2730414	99	54	11,7	cyclictest	13	1	rcu_preempt	08:35:01	3
2730411	99	54	9,6	cyclictest	13	1	rcu_preempt	07:40:00	2
2730411	99	54	7,6	cyclictest	13	1	rcu_preempt	12:10:02	2
2730411	99	54	7,6	cyclictest	13	1	rcu_preempt	11:00:01	2
2730411	99	54	6,10	cyclictest	30	-21	ksoftirqd/2	09:15:00	2
2730411	99	54	2,9	cyclictest	30	-21	ksoftirqd/2	07:55:03	2
2730411	99	54	11,6	cyclictest	13	1	rcu_preempt	09:40:00	2
2730411	99	54	11,6	cyclictest	13	1	rcu_preempt	09:35:00	2
2730411	99	54	11,6	cyclictest	13	1	rcu_preempt	09:10:00	2
2730399	99	54	7,6	cyclictest	13	1	rcu_preempt	11:15:01	0
2730399	99	54	4,7	cyclictest	12	-21	ksoftirqd/0	11:00:01	0
2730399	99	54	2,9	cyclictest	12	-21	ksoftirqd/0	09:35:01	0
2730399	99	54	13,6	cyclictest	13	1	rcu_preempt	11:25:01	0
2730414	99	53	6,6	cyclictest	13	1	rcu_preempt	11:25:02	3
2730414	99	53	14,5	cyclictest	13	1	rcu_preempt	07:20:01	3
2730414	99	53	12,5	cyclictest	13	1	rcu_preempt	07:50:02	3
2730411	99	53	8,6	cyclictest	13	1	rcu_preempt	11:50:02	2
2730411	99	53	7,5	cyclictest	13	1	rcu_preempt	10:15:01	2
2730411	99	53	2,7	cyclictest	30	-21	ksoftirqd/2	07:30:02	2
2730411	99	53	15,5	cyclictest	13	1	rcu_preempt	09:50:01	2
^Timer ^*Wakeup (latency=timer+wakeup+contextswitch)


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This page was last modified on 2021-09-01 - 00:33