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2023-02-07 - 19:25

x86 Intel Atom x6425E @2000 MHz, Linux 5.15.49-rt47 (Profile)

Latency plot of system in rack #e, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot3 (updated Tue Feb 07, 2023 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
266170099670,3cyclictest0-21swapper/210:35:182
266170099660,64cyclictest0-21swapper/211:40:072
2661700996541,20cyclictest2698805-21kworker/2:209:40:182
2661697996151,8cyclictest577039-1kworker/1:1H09:00:221
2661700996042,16cyclictest2727080-21kworker/2:009:45:232
2661700996037,21cyclictest2657112-21kworker/2:007:25:182
2661700996036,21cyclictest2492297-1kworker/2:1H07:14:462
2661700995942,16cyclictest2803719-21kworker/2:011:30:002
2661700995941,16cyclictest2492297-1kworker/2:1H09:20:152
2661700995940,17cyclictest2754299-21kworker/2:110:20:172
2661700995939,18cyclictest2736413-21kworker/2:309:55:212
2661700995937,19cyclictest2740927-21kworker/2:010:10:182
2661700995854,2cyclictest0-21swapper/212:21:162
2661700995843,14cyclictest2803719-21kworker/2:011:39:162
2661700995843,14cyclictest2797710-21kworker/2:111:20:022
2661700995843,14cyclictest2797710-21kworker/2:111:19:472
2661700995843,14cyclictest2754299-21kworker/2:110:19:532
2661700995842,15cyclictest2825307-21kworker/2:212:05:302
2661700995842,15cyclictest2740927-21kworker/2:010:00:192
2661700995842,15cyclictest2657112-21kworker/2:007:39:182
2661700995841,16cyclictest2821300-21kworker/2:111:45:322
266170099580,5cyclictest0-21swapper/210:31:502
266170099580,5cyclictest0-21swapper/210:31:502
2661700995742,14cyclictest2825307-21kworker/2:212:15:162
2661700995742,14cyclictest2803719-21kworker/2:011:25:162
2661700995742,14cyclictest2774937-21kworker/2:110:56:122
2661700995742,14cyclictest2691532-21kworker/2:008:49:352
2661700995742,14cyclictest2688613-21kworker/2:308:34:332
2661700995742,14cyclictest2672706-21kworker/2:208:25:202
2661700995742,14cyclictest2492297-1kworker/2:1H07:20:052
2661700995741,15cyclictest2825307-21kworker/2:212:30:012
2661700995741,15cyclictest2825307-21kworker/2:212:29:452
2661700995741,15cyclictest2774937-21kworker/2:110:45:232
2661700995741,15cyclictest2672706-21kworker/2:208:20:222
2661700995740,16cyclictest2657112-21kworker/2:007:15:252
2661700995740,15cyclictest2492297-1kworker/2:1H09:31:142
2661700995740,15cyclictest2492297-1kworker/2:1H09:31:142
2661700995739,17cyclictest2825307-21kworker/2:211:50:212
2661700995739,17cyclictest2825307-21kworker/2:211:50:212
2661700995736,19cyclictest2492297-1kworker/2:1H09:15:002
2661700995641,14cyclictest2492297-1kworker/2:1H09:35:222
2661700995640,14cyclictest2492297-1kworker/2:1H08:15:242
2661700995639,16cyclictest2788502-21kworker/2:211:10:262
2661700995638,17cyclictest2754299-21kworker/2:110:25:202
2661700995638,16cyclictest2825307-21kworker/2:211:55:222
2661700995540,14cyclictest2825307-21kworker/2:212:37:162
2661700995540,14cyclictest2774937-21kworker/2:111:00:472
2661700995540,14cyclictest2770469-21kworker/2:010:40:002
2661700995540,14cyclictest2740927-21kworker/2:010:05:172
2661700995540,14cyclictest2698805-21kworker/2:209:00:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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