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2025-07-03 - 08:57

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot3s.osadl.org (updated Thu Jul 03, 2025 00:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2915398998681,3cyclictest0-21swapper/021:30:020
2915398997910,27cyclictest131rcu_preempt23:35:030
2915398997265,3cyclictest0-21swapper/022:25:020
2915408996530,8cyclictest30-21ksoftirqd/220:50:012
2915408996530,8cyclictest30-21ksoftirqd/220:50:002
2915408996154,5cyclictest291rcuc/223:05:032
2915408996128,7cyclictest30-21ksoftirqd/223:09:592
2915408996124,11cyclictest30-21ksoftirqd/221:35:022
2915408996012,6cyclictest131rcu_preempt21:55:002
2915408995913,7cyclictest131rcu_preempt23:30:002
2915408995912,10cyclictest131rcu_preempt21:40:022
2915398995952,3cyclictest0-21swapper/000:30:030
291539899591,38cyclictest131rcu_preempt19:15:130
2915408995814,10cyclictest30-21ksoftirqd/220:45:012
2915413995738,15cyclictest272-21dbus-daemon20:40:013
2915408995615,6cyclictest131rcu_preempt00:00:002
2915408995614,7cyclictest131rcu_preempt23:20:012
2915408995614,7cyclictest131rcu_preempt23:20:012
2915408995518,8cyclictest30-21ksoftirqd/221:50:022
2915408995513,7cyclictest131rcu_preempt20:35:022
2915408995513,7cyclictest131rcu_preempt20:35:022
2915398995537,13cyclictest1-21systemd21:55:000
2915398995510,6cyclictest131rcu_preempt20:40:000
2915408995414,8cyclictest30-21ksoftirqd/219:35:022
2915408995414,8cyclictest30-21ksoftirqd/219:35:012
2915408995413,5cyclictest131rcu_preempt21:25:022
2915408995410,7cyclictest131rcu_preempt22:45:022
291540899539,6cyclictest131rcu_preempt20:25:012
291540899538,7cyclictest131rcu_preempt21:05:022
291540899538,7cyclictest131rcu_preempt21:05:012
291540899538,6cyclictest131rcu_preempt22:50:022
291540899538,6cyclictest131rcu_preempt22:50:022
291540899535,10cyclictest30-21ksoftirqd/222:25:012
2915408995312,6cyclictest131rcu_preempt23:50:012
2915408995312,6cyclictest131rcu_preempt23:50:002
291539899535,22cyclictest2929396-21kworker/u8:423:55:010
291539899534,3cyclictest131rcu_preempt23:01:480
291541399522,4cyclictest131rcu_preempt23:05:003
291540899529,5cyclictest131rcu_preempt23:40:012
2915408995213,9cyclictest30-21ksoftirqd/223:45:022
2915408995212,5cyclictest131rcu_preempt21:30:002
2915408995211,6cyclictest131rcu_preempt19:30:012
2915408995211,5cyclictest131rcu_preempt00:17:132
2915408995211,11cyclictest30-21ksoftirqd/222:40:012
291541399515,5cyclictest131rcu_preempt23:40:003
291541399513,7cyclictest37-21ksoftirqd/321:50:033
2915413995116,11cyclictest37-21ksoftirqd/320:25:003
291540899518,6cyclictest131rcu_preempt22:06:362
2915413995028,10cyclictest37-21ksoftirqd/322:19:593
2915413995010,11cyclictest37-21ksoftirqd/321:45:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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