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2025-11-13 - 06:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Wed Nov 12, 2025 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
721199310,30cyclictest6024-21cron09:25:003
721199310,30cyclictest1074-21cron08:05:013
720799300,1cyclictest13939-21cron10:50:012
7205993028,1cyclictest0-21swapper/107:25:001
720199300,29cyclictest30856-21sh08:00:000
721199290,28cyclictest4270-21perf10:30:003
721199290,1cyclictest0-21swapper/307:30:013
7207992927,1cyclictest609-21dbus-daemon07:25:002
7207992927,1cyclictest13073-21sendmail-msp09:40:002
720599290,28cyclictest0-21swapper/111:55:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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