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2026-06-11 - 09:13

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot5s.osadl.org (updated Thu Jun 11, 2026 00:44:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1812992922,4cyclictest0-21swapper/321:14:483
181299270,22cyclictest2343-21sh21:17:143
1812992621,5cyclictest27863-21diskmemload23:13:263
1812992620,5cyclictest0-21swapper/300:29:283
181299260,1cyclictest0-21swapper/321:59:593
180399262,23cyclictest4212-21cat21:19:241
1812992523,2cyclictest0-21swapper/300:31:573
1812992522,3cyclictest0-21swapper/323:01:383
1812992522,3cyclictest0-21swapper/322:08:473
1812992521,4cyclictest27863-21diskmemload22:35:103
1812992520,4cyclictest0-21swapper/321:52:253
1812992519,5cyclictest2327-21sh22:47:133
1812992517,5cyclictest27863-21diskmemload21:48:463
181299250,24cyclictest0-21swapper/323:38:243
181299250,24cyclictest0-21swapper/322:55:083
181299250,24cyclictest0-21swapper/321:41:203
181299250,20cyclictest0-21swapper/323:06:473
181299250,1cyclictest0-21swapper/323:15:163
181299250,0cyclictest0-21swapper/323:50:353
181299250,0cyclictest0-21swapper/322:43:063
1808992521,0cyclictest0-21swapper/221:24:352
1803992523,2cyclictest8491-21sh23:24:221
180399250,25cyclictest0-21swapper/123:39:271
180399250,24cyclictest27863-21diskmemload23:08:181
180099251,24cyclictest141rcuc/023:22:390
180099251,23cyclictest27863-21diskmemload21:19:240
180099250,24cyclictest27065-21sh23:09:500
180099250,24cyclictest0-21swapper/000:30:280
1812992421,3cyclictest0-21swapper/322:27:483
1812992420,4cyclictest0-21swapper/323:56:563
1812992420,3cyclictest0-21swapper/300:38:553
1812992420,3cyclictest0-21swapper/300:03:213
181299240,23cyclictest27863-21diskmemload00:14:293
181299240,23cyclictest27863-21diskmemload00:14:293
181299240,0cyclictest27863-21diskmemload23:45:523
181299240,0cyclictest0-21swapper/321:36:513
181299240,0cyclictest0-21swapper/321:28:473
1808992423,1cyclictest0-21swapper/223:54:172
1808992423,1cyclictest0-21swapper/222:33:542
1808992421,2cyclictest0-21swapper/223:43:522
1808992420,3cyclictest0-21swapper/223:17:402
1808992420,3cyclictest0-21swapper/200:30:362
180899240,23cyclictest27863-21diskmemload00:02:312
180899240,23cyclictest0-21swapper/222:24:302
1803992422,1cyclictest428-21rm23:45:471
1803992422,1cyclictest18982-21ssh23:03:141
1803992422,1cyclictest11594-21rm23:26:011
1803992421,2cyclictest28426-21ssh22:10:411
180399241,1cyclictest9031-21ssh22:23:381
180399240,24cyclictest0-21swapper/100:07:341
180399240,23cyclictest662-21cron21:15:011
180399240,23cyclictest0-21swapper/123:51:121
180399240,0cyclictest0-21swapper/100:33:371
1800992423,1cyclictest0-21swapper/021:30:300
1800992422,1cyclictest6002-21sh23:51:120
180099240,23cyclictest27863-21diskmemload22:54:510
180099240,23cyclictest27863-21diskmemload21:37:400
180099240,23cyclictest0-21swapper/000:04:240
180099240,1cyclictest18522-21ssh23:33:160
180099240,0cyclictest27863-21diskmemload21:48:240
1812992323,0cyclictest0-21swapper/322:19:113
1812992321,1cyclictest0-21swapper/322:10:013
1812992321,1cyclictest0-21swapper/321:33:263
1812992320,3cyclictest0-21swapper/323:20:113
1812992319,4cyclictest27863-21diskmemload21:21:213
1812992319,4cyclictest0-21swapper/321:09:243
1812992319,4cyclictest0-21swapper/300:06:313
1812992319,3cyclictest0-21swapper/323:40:113
1812992318,4cyclictest0-21swapper/320:44:243
181299230,2cyclictest8636-21idleruntime-cro20:30:003
181299230,23cyclictest0-21swapper/300:16:093
181299230,22cyclictest0-21swapper/322:21:313
181299230,20cyclictest27863-21diskmemload22:53:273
181299230,0cyclictest0-21swapper/323:25:493
1808992323,0cyclictest0-21swapper/223:48:352
1808992323,0cyclictest0-21swapper/223:36:102
1808992323,0cyclictest0-21swapper/221:30:582
1808992323,0cyclictest0-21swapper/200:20:382
1808992323,0cyclictest0-21swapper/200:10:142
1808992323,0cyclictest0-21swapper/200:10:142
1808992322,1cyclictest7089-21ssh22:51:252
1808992321,1cyclictest0-21swapper/221:45:492
1808992321,1cyclictest0-21swapper/221:35:542
1808992321,1cyclictest0-21swapper/221:26:262
1808992321,1cyclictest0-21swapper/221:16:022
1808992320,2cyclictest32756-21ssh22:14:342
1808992320,2cyclictest27863-21diskmemload21:54:292
1808992320,0cyclictest0-21swapper/223:55:132
1808992319,4cyclictest0-21swapper/223:05:032
180899230,23cyclictest27863-21diskmemload23:31:362
180899230,22cyclictest5900-21ssh23:20:172
180899230,22cyclictest27863-21diskmemload22:46:052
180899230,22cyclictest22828-21sh22:35:172
180899230,22cyclictest0-21swapper/223:01:352
180899230,1cyclictest0-21swapper/223:14:102
180899230,0cyclictest0-21swapper/222:55:152
180899230,0cyclictest0-21swapper/200:25:342
1803992323,0cyclictest27863-21diskmemload22:00:461
1803992323,0cyclictest0-21swapper/123:13:081
1803992323,0cyclictest0-21swapper/122:38:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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