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2021-07-26 - 19:31

Intel(R) Core(TM) i3-8145UE CPU @ 2.20GHz, Linux 5.10.27-rt36 (Profile)

Latency plot of system in rack #e, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Mon Jul 26, 2021 12:44:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9195993528,3cyclictest2515-21diskmemload11:14:223
9195993332,1cyclictest11976-21kworker/3:110:25:163
919599330,32cyclictest2515-21diskmemload11:21:353
919299332,18cyclictest0-21swapper/210:26:202
919299330,32cyclictest0-21swapper/210:10:182
918899330,32cyclictest0-21swapper/110:45:221
918899330,32cyclictest0-21swapper/107:20:181
9183993332,1cyclictest224-1kworker/0:1H11:20:160
918399330,32cyclictest0-21swapper/008:30:210
9195993231,1cyclictest36-1kworker/3:0H08:55:213
9195993231,1cyclictest36-1kworker/3:0H08:25:273
9195993228,3cyclictest15578-21ssh12:08:493
9195993227,4cyclictest0-21swapper/310:10:283
919599320,29cyclictest0-21swapper/309:32:053
919599320,1cyclictest2515-21diskmemload10:55:573
9192993227,4cyclictest0-21swapper/210:48:502
9188993231,1cyclictest100-1kworker/1:1H12:25:171
918899320,31cyclictest0-21swapper/111:35:211
9183993231,1cyclictest224-1kworker/0:1H08:10:290
9183993231,1cyclictest224-1kworker/0:1H07:40:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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