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2024-07-27 - 07:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Sat Jul 27, 2024 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31642994545,0cyclictest24213-21diskmemload21:50:241
31647993232,0cyclictest0-21swapper/322:32:273
3164299310,30cyclictest0-21swapper/123:37:371
31647993028,1cyclictest0-21swapper/323:50:193
3164799300,29cyclictest32065-21taskset21:50:593
3164799300,29cyclictest31681-21cron23:35:013
31642993028,1cyclictest24213-21diskmemload21:45:151
3164299300,29cyclictest24213-21diskmemload22:41:181
3164299300,29cyclictest21684-21/usr/sbin/munin22:50:181
31640993030,0cyclictest24213-21diskmemload22:29:360
31640993028,1cyclictest575-21dbus-daemon23:50:000
31640993027,2cyclictest6022-21basename21:25:010
3164099300,30cyclictest16725-21taskset23:52:280
3164099300,29cyclictest5474-21awk23:40:170
3164099300,1cyclictest308-21systemd-journal23:00:010
31647992928,1cyclictest24213-21diskmemload23:35:113
3164799290,28cyclictest24213-21diskmemload22:00:163
3164799290,28cyclictest23063-21munin-run00:00:003
3164799290,28cyclictest19335-21ssh22:46:233
3164799290,28cyclictest16967-21hddtemp_smartct22:10:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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