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2024-05-27 - 18:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Mon May 27, 2024 00:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1940996530,0cyclictest0-21swapper/119:12:141
1949993332,1cyclictest4565-21lspci19:12:143
194099322,29cyclictest30996-21sh21:14:301
193599320,31cyclictest558-21irqbalance22:20:480
1944993129,1cyclictest23814-21sort00:40:022
194499310,30cyclictest23839-21ssh23:29:202
1940993129,1cyclictest0-21swapper/120:09:261
1940993129,1cyclictest0-21swapper/100:15:151
194099311,29cyclictest26744-21apt-get21:45:111
194099310,30cyclictest7446-21ssh21:59:431
194099310,30cyclictest16936-21gltestperf22:45:161
1935993129,1cyclictest561-21dbus-daemon00:40:020
193599310,30cyclictest2411-21systemd-journal22:15:010
1949993028,1cyclictest0-21swapper/322:10:473
1949993028,1cyclictest0-21swapper/300:05:013
194999301,29cyclictest26720-21diskmemload21:54:443
194999300,2cyclictest15850-21sh21:32:153
194999300,29cyclictest8280-21ssh21:25:113
194999300,29cyclictest2762-21/usr/sbin/munin22:30:233
194999300,29cyclictest26720-21diskmemload22:50:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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