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2023-12-10 - 15:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Sun Dec 10, 2023 00:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29177993328,0cyclictest0-21swapper/219:35:242
29172993328,4cyclictest0-21swapper/100:05:021
2917299330,32cyclictest0-21swapper/122:31:491
29177993229,0cyclictest20810-21diskmemload23:53:532
29177993228,3cyclictest0-21swapper/223:12:022
2917799320,29cyclictest20810-21diskmemload21:50:322
2917799320,29cyclictest0-21swapper/221:17:372
2917799320,29cyclictest0-21swapper/200:25:162
2917799320,1cyclictest10027-21sh00:18:202
2917799320,0cyclictest0-21swapper/221:26:092
29172993228,3cyclictest20810-21diskmemload22:24:021
29172993228,3cyclictest0-21swapper/122:12:051
2917299320,31cyclictest20810-21diskmemload22:06:381
2917299320,31cyclictest0-21swapper/123:26:471
2917299320,31cyclictest0-21swapper/123:17:091
2917299320,29cyclictest0-21swapper/122:54:171
2917299320,28cyclictest0-21swapper/122:47:351
29182993129,1cyclictest30686-21munin-run21:20:003
2918299310,30cyclictest8317-21ssh22:02:163
29177993128,0cyclictest0-21swapper/222:31:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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