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2023-01-30 - 12:52

x86 Intel Core i3-8145UE @2200 MHz, Linux 5.10.27-rt36 (Profile)

Latency plot of system in rack #e, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot5.osadl.org (updated Mon Jan 30, 2023 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5079993433,1cyclictest58550irq/126-eno122:26:240
5081993230,1cyclictest27272-21sed22:10:242
5082993129,1cyclictest7892-21df00:00:223
5082993129,1cyclictest7373-21sh19:15:013
5080993131,0cyclictest29107-21diskmemload22:52:161
5080993129,1cyclictest0-21swapper/121:15:161
5079993128,2cyclictest9266-21cron23:30:010
5082993028,1cyclictest28784-21sh22:45:013
508299300,29cyclictest29107-21diskmemload22:54:363
508299300,29cyclictest29107-21diskmemload22:16:243
508299300,29cyclictest29107-21diskmemload21:25:523
508299300,29cyclictest14663-21apt-get19:30:203
508299300,29cyclictest0-21swapper/323:20:173
508299300,29cyclictest0-21swapper/323:12:123
5081993030,0cyclictest0-21swapper/222:31:492
508199301,0cyclictest29107-21diskmemload22:17:242
508199300,29cyclictest8057-21ssh00:00:252
508199300,29cyclictest584-21gdbus23:00:002
508199300,29cyclictest29107-21diskmemload21:10:412
508199300,29cyclictest29107-21diskmemload00:11:462
508199300,29cyclictest0-21swapper/222:00:052
508199300,29cyclictest0-21swapper/221:45:162
508199300,29cyclictest0-21swapper/200:15:022
5080993028,1cyclictest754-21runrttasks23:48:061
5080993028,1cyclictest19746-21apt-get23:40:201
5080993028,1cyclictest0-21swapper/120:10:011
508099300,29cyclictest29107-21diskmemload00:31:561
508099300,29cyclictest0-21swapper/123:59:321
508099300,29cyclictest0-21swapper/123:11:151
508099300,29cyclictest0-21swapper/122:25:141
508099300,29cyclictest0-21swapper/121:31:121
508099300,29cyclictest0-21swapper/121:00:211
508099300,29cyclictest0-21swapper/100:17:031
508099300,1cyclictest29107-21diskmemload00:38:511
507999300,30cyclictest0-21swapper/022:34:460
507999300,29cyclictest29107-21diskmemload23:55:030
507999300,29cyclictest29107-21diskmemload22:45:190
507999300,29cyclictest0-21swapper/021:50:210
507999300,29cyclictest0-21swapper/021:42:470
507999300,29cyclictest0-21swapper/021:27:170
507999300,1cyclictest0-21swapper/021:05:180
507999300,0cyclictest0-21swapper/022:21:570
5082992929,0cyclictest0-21swapper/322:02:133
5082992927,1cyclictest13005-21irqstats23:00:253
508299290,29cyclictest29107-21diskmemload23:56:203
508299290,29cyclictest29107-21diskmemload23:37:013
508299290,29cyclictest29107-21diskmemload23:30:563
508299290,29cyclictest29107-21diskmemload22:48:053
508299290,29cyclictest29107-21diskmemload22:30:433
508299290,29cyclictest29107-21diskmemload21:15:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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