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2024-05-30 - 02:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Wed May 29, 2024 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1593463994671,463cyclictest1868076-21kworker/u8:0+efi_rts_wq12:10:140
1593463994650,462cyclictest4059144-21kworker/u8:1+efi_rts_wq07:52:150
1593463994611,456cyclictest4059144-21kworker/u8:1+efi_rts_wq09:10:140
1593468994581,453cyclictest2028183-21kworker/u8:0+efi_rts_wq12:35:131
1593470994571,453cyclictest4059144-21kworker/u8:1+efi_rts_wq10:17:442
1593463994570,453cyclictest4052417-21kworker/u8:3+efi_rts_wq09:05:170
1593463994570,453cyclictest1897779-21kworker/u8:3+efi_rts_wq11:07:530
1593463994570,453cyclictest1868076-21kworker/u8:0+efi_rts_wq11:55:130
1593470994551,451cyclictest1581149-21kworker/u8:2+efi_rts_wq08:25:132
1593470994510,448cyclictest1897779-21kworker/u8:3+efi_rts_wq11:40:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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