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2024-04-26 - 10:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Fri Apr 26, 2024 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1928491994771,472cyclictest2251856-21kworker/u8:2+efi_rts_wq23:55:130
1928491994701,465cyclictest2139283-21kworker/u8:0+efi_rts_wq23:20:130
1928491994671,462cyclictest2016548-21kworker/u8:1+efi_rts_wq22:00:120
1928497994630,459cyclictest3070299-21kworker/u8:0+efi_rts_wq19:30:111
1928491994630,459cyclictest2238470-21kworker/u8:4+efi_rts_wq23:05:270
1928491994610,458cyclictest2139283-21kworker/u8:0+efi_rts_wq22:55:130
1928491994610,457cyclictest2016548-21kworker/u8:1+efi_rts_wq21:50:130
1928497994600,457cyclictest2016548-21kworker/u8:1+efi_rts_wq22:00:121
1928503994590,456cyclictest2139283-21kworker/u8:0+efi_rts_wq22:55:252
1928503994590,455cyclictest2076156-21kworker/u8:4+efi_rts_wq21:45:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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