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2026-04-17 - 05:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Fri Apr 17, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
182885992825,1cyclictest0-21swapper/323:25:013
182885992825,1cyclictest0-21swapper/300:19:593
182885992522,1cyclictest0-21swapper/322:20:013
182885992319,1cyclictest0-21swapper/320:40:003
182885992219,1cyclictest0-21swapper/321:25:003
182885992118,1cyclictest0-21swapper/323:20:003
182885992118,1cyclictest0-21swapper/322:45:183
182885992118,1cyclictest0-21swapper/320:00:243
182885992117,1cyclictest0-21swapper/321:45:173
18288599211,15cyclictest243169-21chrt19:55:123
182885992110,7cyclictest6398852sleep300:24:343
4400172201,10sleep1440051-21/usr/sbin/munin22:15:141
182885992017,1cyclictest0-21swapper/300:30:233
18288599201,14cyclictest294187-21taskset20:33:293
18288599201,13cyclictest470764-21chrt22:35:113
6419712190,9sleep0643572-21cut00:25:200
2543352190,1sleep10-21swapper/120:00:191
182885991916,1cyclictest0-21swapper/323:35:243
182885991916,1cyclictest0-21swapper/322:40:023
182885991916,1cyclictest0-21swapper/321:55:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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