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2026-02-09 - 15:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackfslot0.osadl.org (updated Mon Feb 09, 2026 00:55:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137456099171119,49cyclictest0-21swapper/2519:15:1518
137454699171120,47cyclictest0-21swapper/1519:15:167
13745579916682,57cyclictest0-21swapper/2222:20:1615
13745579916682,57cyclictest0-21swapper/2222:20:1615
13745579916576,58cyclictest187823-21kworker/u64:2+efi_rts_wq00:05:1515
1374557991642,160cyclictest0-21swapper/2219:15:1515
13745579916383,46cyclictest187823-21kworker/u64:2+efi_rts_wq21:00:1915
13745579916383,46cyclictest187823-21kworker/u64:2+efi_rts_wq21:00:1915
13745069916374,65cyclictest0-21swapper/319:25:1623
1374566991610,91cyclictest0-21swapper/3119:25:1625
13745549916182,65cyclictest0-21swapper/1921:50:1711
13745489916189,44cyclictest0-21swapper/1619:25:178
13745489916188,54cyclictest0-21swapper/1619:40:158
13745489916188,54cyclictest0-21swapper/1619:40:158
13745529916084,65cyclictest0-21swapper/1720:00:169
13745529916084,65cyclictest0-21swapper/1720:00:169
137453499160114,43cyclictest0-21swapper/1219:15:154
13745039915779,57cyclictest0-21swapper/219:25:1712
13744999915777,8cyclictest0-21swapper/121:08:561
13744999915777,8cyclictest0-21swapper/121:08:561
13745579915678,59cyclictest0-21swapper/2221:50:1715
13745549915584,68cyclictest0-21swapper/1921:10:1811
13745549915584,68cyclictest0-21swapper/1921:10:1711
13745549915581,46cyclictest0-21swapper/1900:05:1611
13745539915376,6cyclictest0-21swapper/1822:40:1610
137451599153124,8cyclictest0-21swapper/622:10:1528
137451599153124,8cyclictest0-21swapper/622:10:1528
13745149915378,52cyclictest0-21swapper/519:48:3627
13745149915378,52cyclictest0-21swapper/519:48:3627
13745579915277,49cyclictest0-21swapper/2223:15:1815
13745579915277,49cyclictest0-21swapper/2223:15:1815
13745539915285,57cyclictest0-21swapper/1819:53:3710
13745539915285,57cyclictest0-21swapper/1819:53:3710
13745539915283,48cyclictest0-21swapper/1823:56:0610
13745229915284,6cyclictest0-21swapper/821:08:5630
13745229915284,6cyclictest0-21swapper/821:08:5630
13745039915277,53cyclictest0-21swapper/219:40:1612
13745039915277,53cyclictest0-21swapper/219:40:1512
13745579915177,53cyclictest0-21swapper/2219:55:1615
13745579915177,53cyclictest0-21swapper/2219:55:1615
13745549915177,43cyclictest0-21swapper/1919:30:1611
13745549915177,43cyclictest0-21swapper/1919:30:1611
13745639915073,49cyclictest0-21swapper/2823:35:1521
13745639915073,49cyclictest0-21swapper/2823:35:1521
13745549915083,43cyclictest0-21swapper/1923:15:1811
13745549915083,43cyclictest0-21swapper/1923:15:1811
13745489914973,73cyclictest0-21swapper/1623:45:158
137451599149122,8cyclictest0-21swapper/620:53:5328
137451599149122,8cyclictest0-21swapper/620:53:5328
13745579914862,66cyclictest0-21swapper/2220:35:1615
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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