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2026-01-24 - 07:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot5.osadl.org (updated Sat Jan 24, 2026 00:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2214099966926,35cyclictest9270-21kworker/0:6+events_freezable_power_19:17:460
2214299804794,5cyclictest0-21swapper/219:17:452
2214199802787,8cyclictest0-21swapper/119:17:451
2214099795746,42cyclictest19071-21kworker/0:5+events_freezable_power_20:45:300
2214399794787,3cyclictest0-21swapper/319:17:453
2214099785746,34cyclictest8863-21kworker/0:2+events_freezable_power_22:46:080
2214099783736,40cyclictest9270-21kworker/0:6+events_freezable_power_21:40:200
2214099783736,40cyclictest9270-21kworker/0:6+events_freezable_power_21:40:200
2214099776736,35cyclictest11500-21kworker/0:3+events_freezable_power_22:02:160
2214099774733,36cyclictest8863-21kworker/0:2+events_freezable_power_00:35:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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