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2026-01-25 - 11:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackfslot5.osadl.org (updated Sun Jan 25, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
212699939927,7cyclictest0-21swapper/120:42:091
212699939927,7cyclictest0-21swapper/120:42:081
212799935925,5cyclictest0-21swapper/220:42:082
212799935925,5cyclictest0-21swapper/220:42:082
212699934922,7cyclictest0-21swapper/122:09:521
212799930920,5cyclictest0-21swapper/222:09:532
212599901879,17cyclictest12336-21kworker/0:0+events_freezable_power_20:42:080
212599901879,17cyclictest12336-21kworker/0:0+events_freezable_power_20:42:080
212599896875,16cyclictest12336-21kworker/0:0+events_freezable_power_22:09:530
212899842833,5cyclictest0-21swapper/320:42:093
212899842833,5cyclictest0-21swapper/320:42:093
212899838828,5cyclictest0-21swapper/322:09:523
212699770760,5cyclictest0-21swapper/100:10:301
212799766758,3cyclictest0-21swapper/200:10:312
212699756743,8cyclictest0-21swapper/120:20:131
212699756743,8cyclictest0-21swapper/120:20:121
212799752741,5cyclictest0-21swapper/220:20:122
212799752741,5cyclictest0-21swapper/220:20:122
212699747734,8cyclictest0-21swapper/100:32:271
212799743732,5cyclictest0-21swapper/200:32:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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