You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-12 - 11:11
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sat Jul 12, 2025 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3759834997613,20cyclictest0-21swapper/623:35:206
3759829997517,19cyclictest191rcu_preempt22:40:191
3759834997336,18cyclictest781ktimers/600:09:156
3759834997132,38cyclictest0-21swapper/623:25:306
3759834996931,38cyclictest0-21swapper/623:31:316
3759834996930,39cyclictest0-21swapper/600:37:276
3759834996831,18cyclictest3850955-21gltestperf21:50:196
3759834996729,19cyclictest0-21swapper/621:35:116
3759834996728,19cyclictest0-21swapper/620:58:556
375983499657,39cyclictest0-21swapper/622:41:426
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional