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2024-05-04 - 05:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat May 04, 2024 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1749221350,0sleep120-21swapper/1222:27:484
1749221350,0sleep120-21swapper/1222:27:484
3264821290,1sleep1232640-21sshd22:32:534
3264821290,1sleep1232640-21sshd22:32:534
250532126106,16sleep140-21swapper/1419:10:466
25118212394,24sleep30-21swapper/319:11:399
1759021190,5sleep132565899cyclictest21:31:555
2436721180,0sleep20-21swapper/223:29:098
24954210895,9sleep50-21swapper/519:09:1711
25155210791,10sleep40-21swapper/419:12:1210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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