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2023-02-05 - 11:04

x86 Intel Core i7-X990 @3467 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #c, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackcslot1.osadl.org (updated Sun Feb 05, 2023 00:48:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3907991100,98rtkit-daemon0-21swapper/1119:10:003
2770027869,6sleep50-21swapper/519:05:297
2795627667,6sleep30-21swapper/319:09:035
2721327157,7sleep10-21swapper/119:05:241
2775427055,12sleep40-21swapper/419:06:166
2798826857,8sleep80-21swapper/819:09:3310
2785226859,6sleep90-21swapper/919:07:3311
2798726757,7sleep70-21swapper/719:09:319
2565726758,6sleep20-21swapper/219:05:134
2799026657,6sleep100-21swapper/1019:09:342
2790526454,7sleep60-21swapper/619:08:188
311222590,1sleep20-21swapper/222:46:504
106062590,1sleep00-21swapper/023:35:170
84532550,2sleep72847999cyclictest00:09:419
180952550,0sleep80-21swapper/821:21:5910
2773725445,6sleep00-21swapper/019:05:590
2846799255,15cyclictest0-21swapper/500:40:017
2848499244,15cyclictest0-21swapper/821:10:0110
2846799244,15cyclictest0-21swapper/523:00:017
2849199234,14cyclictest0-21swapper/923:15:0111
2849199225,16cyclictest0-21swapper/900:25:0111
2849199224,13cyclictest0-21swapper/922:20:0211
2849199224,13cyclictest0-21swapper/920:35:0111
2847999224,13cyclictest0-21swapper/700:40:019
2849199210,20cyclictest0-21swapper/919:29:5711
2849199210,20cyclictest0-21swapper/919:29:5711
2848499213,13cyclictest0-21swapper/822:15:0010
2846799214,12cyclictest0-21swapper/522:40:017
2845599214,13cyclictest0-21swapper/322:55:015
2845599213,13cyclictest0-21swapper/322:25:015
2850299204,11cyclictest0-21swapper/1121:35:013
2849199203,12cyclictest0-21swapper/923:40:0111
2848499203,12cyclictest0-21swapper/821:55:0110
2847999203,12cyclictest0-21swapper/722:06:599
2847999200,13cyclictest0-21swapper/700:27:169
2845599204,11cyclictest0-21swapper/322:35:025
2845099203,13cyclictest0-21swapper/223:10:014
2850299194,10cyclictest0-21swapper/1123:00:013
2850299193,12cyclictest0-21swapper/1122:50:013
2849199193,12cyclictest0-21swapper/921:50:0011
2849199193,11cyclictest0-21swapper/920:15:0111
2848499190,13cyclictest0-21swapper/823:49:0710
2848499190,13cyclictest0-21swapper/823:01:0910
2848499190,12cyclictest0-21swapper/800:15:1210
2847999190,18cyclictest0-21swapper/700:31:199
2845599193,12cyclictest0-21swapper/321:30:015
2845099193,13cyclictest0-21swapper/200:35:014
28443991916,3cyclictest0-21swapper/100:35:211
2850299184,10cyclictest0-21swapper/1122:30:013
2850299183,11cyclictest0-21swapper/1100:15:013
2849199183,11cyclictest0-21swapper/923:30:0211
2848499183,11cyclictest0-21swapper/823:20:0110
2848499180,2cyclictest0-21swapper/800:36:0310
2848499180,12cyclictest0-21swapper/821:35:1710
2848499180,12cyclictest0-21swapper/800:05:4510
2846799184,12cyclictest0-21swapper/523:35:017
2845599183,11cyclictest0-21swapper/321:25:025
2844399180,17cyclictest0-21swapper/100:31:571
2850299174,10cyclictest0-21swapper/1121:25:013
2848499178,3cyclictest0-21swapper/823:13:0310
2848499171,15cyclictest0-21swapper/823:25:3010
2848499170,3cyclictest0-21swapper/822:42:4210
2848499170,2cyclictest0-21swapper/823:44:4110
2848499170,2cyclictest0-21swapper/800:30:5610
2848499170,16cyclictest0-21swapper/800:28:2910
2848499170,12cyclictest0-21swapper/800:00:2110
2847999173,11cyclictest0-21swapper/722:00:009
2847999173,11cyclictest0-21swapper/720:40:019
2847299173,11cyclictest0-21swapper/621:25:018
2847299172,12cyclictest0-21swapper/600:15:018
12962170,0sleep50-21swapper/519:15:177
12962170,0sleep50-21swapper/519:15:177
390799160,4rtkit-daemon9102-21ssh21:48:197
2849699160,15cyclictest0-21swapper/1000:19:582
2849199161,11cyclictest0-21swapper/922:45:0211
2849199161,11cyclictest0-21swapper/920:30:0211
2849199160,15cyclictest0-21swapper/900:17:5411
2848499162,6cyclictest0-21swapper/822:56:1010
2848499160,2cyclictest0-21swapper/819:10:1310
2848499160,2cyclictest0-21swapper/819:10:1310
2848499160,2cyclictest0-21swapper/800:10:0610
2848499160,1cyclictest7551-21ssh23:31:2610
2848499160,11cyclictest30866-21ssh23:57:3810
2847999162,11cyclictest0-21swapper/721:40:029
2847299163,9cyclictest0-21swapper/619:35:018
2847299163,10cyclictest0-21swapper/621:50:018
2846299163,9cyclictest0-21swapper/423:25:016
2845599163,10cyclictest0-21swapper/319:15:015
2845599163,10cyclictest0-21swapper/319:15:015
28491991511,3cyclictest0-21swapper/919:36:1211
28491991511,3cyclictest0-21swapper/900:33:4611
2849199150,14cyclictest0-21swapper/921:25:0111
2849199150,14cyclictest0-21swapper/900:06:2911
2847299153,9cyclictest0-21swapper/620:10:018
28472991511,3cyclictest0-21swapper/623:52:318
28472991511,3cyclictest0-21swapper/600:10:238
2847299150,14cyclictest0-21swapper/619:37:208
2846799153,9cyclictest0-21swapper/523:30:027
28467991511,3cyclictest0-21swapper/500:05:017
2846799150,14cyclictest0-21swapper/500:34:047
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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