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2022-11-28 - 02:29

x86 Intel Celeron G3900 @2800 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Sun Nov 27, 2022 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2441728052,8sleep00-21swapper/007:06:520
2438227258,9sleep10-21swapper/107:06:321
190602670,0sleep10-21swapper/112:03:001
24745991715,1cyclictest20359-21ssh10:19:581
24745991715,1cyclictest202012sleep111:13:041
24745991710,0cyclictest0-21swapper/107:30:421
24744991715,1cyclictest252702sleep008:33:200
24744991715,1cyclictest11793-21sh07:58:230
24744991713,4cyclictest0-21swapper/007:20:020
24744991710,7cyclictest0-21swapper/008:46:180
24744991710,7cyclictest0-21swapper/007:41:020
24744991710,6cyclictest0-21swapper/008:48:260
24745991616,0cyclictest0-21swapper/109:56:081
24745991615,1cyclictest0-21swapper/110:30:011
24744991615,1cyclictest8515-21ssh11:44:320
24744991615,0cyclictest21497-21chrt09:30:520
24744991612,4cyclictest0-21swapper/012:36:580
24744991612,4cyclictest0-21swapper/008:00:180
24744991612,4cyclictest0-21swapper/007:43:460
24744991612,4cyclictest0-21swapper/007:08:340
24744991610,6cyclictest0-21swapper/009:23:060
24744991610,6cyclictest0-21swapper/008:53:340
24744991610,6cyclictest0-21swapper/008:18:540
24744991610,1cyclictest0-21swapper/011:12:140
24744991610,0cyclictest0-21swapper/009:10:460
24745991515,0cyclictest7962-21ssh10:00:231
24745991515,0cyclictest0-21swapper/111:51:131
24745991515,0cyclictest0-21swapper/111:19:581
24745991515,0cyclictest0-21swapper/110:43:331
24745991515,0cyclictest0-21swapper/110:13:191
24745991515,0cyclictest0-21swapper/108:02:111
24745991515,0cyclictest0-21swapper/107:49:391
24745991513,1cyclictest633-21nscd10:39:161
24745991510,0cyclictest0-21swapper/110:48:541
24745991510,0cyclictest0-21swapper/109:49:461
24745991510,0cyclictest0-21swapper/109:37:341
24745991510,0cyclictest0-21swapper/108:39:461
24744991515,0cyclictest10045-21ssh10:55:370
24744991515,0cyclictest0-21swapper/011:24:550
24744991515,0cyclictest0-21swapper/011:17:140
24744991513,1cyclictest850-21expr11:33:410
24744991512,3cyclictest0-21swapper/009:16:500
24744991512,3cyclictest0-21swapper/008:34:140
24744991511,4cyclictest0-21swapper/010:39:220
24744991511,4cyclictest0-21swapper/010:25:220
24744991510,5cyclictest0-21swapper/010:59:300
24744991510,5cyclictest0-21swapper/010:52:460
24744991510,5cyclictest0-21swapper/009:23:460
24744991510,5cyclictest0-21swapper/007:34:500
24744991510,5cyclictest0-21swapper/007:15:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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