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2025-07-04 - 07:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 04, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3250699230,18cyclictest0-21swapper/022:05:170
3250799220,4cyclictest0-21swapper/122:08:401
3250799220,4cyclictest0-21swapper/119:20:351
3250699214,11cyclictest0-21swapper/019:27:210
32508992014,5cyclictest0-21swapper/219:23:502
3250899193,15cyclictest28-21ksoftirqd/222:01:492
32508991917,1cyclictest0-21swapper/221:30:152
3250899190,18cyclictest1555-21lxd20:30:542
3250899190,16cyclictest4581-21H212:26:332
3250899190,16cyclictest4528-21H212:26:332
3250899190,16cyclictest0-21swapper/200:00:222
32507991917,1cyclictest21-21ksoftirqd/123:54:061
3250799190,17cyclictest4534-21H212:26:331
3250799190,16cyclictest4581-21H212:26:331
3250699192,16cyclictest7694-21cut20:20:150
32506991916,2cyclictest4593-21H212:26:330
32506991916,2cyclictest4538-21H212:26:330
32506991916,2cyclictest4526-21H212:26:330
3250699190,18cyclictest0-21swapper/020:35:150
3250899182,15cyclictest0-21swapper/221:19:542
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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