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2025-05-09 - 14:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri May 09, 2025 00:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3147721360,7sleep0513799cyclictest22:25:150
98342590,3sleep00-21swapper/023:55:210
2847191590,4ptp4l0-21swapper/222:13:032
2847191580,5ptp4l0-21swapper/121:40:291
2847191570,4ptp4l0-21swapper/020:45:020
2847191560,6ptp4l4707-21chrt19:08:123
2847191560,5ptp4l0-21swapper/119:46:591
2847191560,4ptp4l0-21swapper/122:50:201
2847191550,5ptp4l0-21swapper/122:45:161
2847191550,4ptp4l0-21swapper/100:10:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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