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2024-04-27 - 01:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Apr 26, 2024 12:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1176911800,5ptp4l0-21swapper/107:05:411
1176911720,8ptp4l0-21swapper/207:05:172
1176911610,15ptp4l0-21swapper/307:06:483
1129621450,3sleep02396499cyclictest11:20:260
1176911330,14ptp4l0-21swapper/007:06:030
117691760,5ptp4l2396499cyclictest08:45:140
117691690,4ptp4l557-21ls08:40:240
290942630,2sleep00-21swapper/007:20:120
117691630,2ptp4l0-21swapper/009:30:130
235492620,2sleep00-21swapper/009:30:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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