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2025-07-01 - 23:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jul 01, 2025 12:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2847191690,4ptp4l4834-21/usr/sbin/munin09:40:231
30945996324,6cyclictest9-21ksoftirqd/012:05:190
2847191600,4ptp4l0-21swapper/008:35:190
2847191590,5ptp4l0-21swapper/210:35:262
2847191590,4ptp4l0-21swapper/208:55:402
2847191590,3ptp4l0-21swapper/211:50:262
2847191580,4ptp4l0-21swapper/209:06:122
2847191580,3ptp4l0-21swapper/108:58:211
30945995624,9cyclictest9-21ksoftirqd/009:00:000
30945995623,4cyclictest9-21ksoftirqd/010:40:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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