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2025-07-19 - 00:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Jul 18, 2025 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
45272226160,21sleep20-21swapper/207:06:012
47052209174,23sleep10-21swapper/107:08:201
137191208174,22phc2sys0-21swapper/307:06:543
45352200168,22sleep00-21swapper/007:06:070
1835021610,3sleep2513599cyclictest11:00:002
1291421280,4sleep3513699cyclictest11:55:133
5136996830,9cyclictest41-21ksoftirqd/309:46:173
5136996632,4cyclictest41-21ksoftirqd/311:00:003
5136996331,7cyclictest41-21ksoftirqd/311:10:003
5136996231,7cyclictest41-21ksoftirqd/308:35:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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