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2024-04-26 - 16:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Apr 26, 2024 12:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1043124380,4sleep30-21swapper/307:05:303
895321220,8sleep31145399cyclictest11:40:193
1103628867,10sleep10-21swapper/107:08:281
1098028514,58sleep20-21swapper/207:07:452
57698830,13rtkit-daemon0-21swapper/007:08:320
825591800,10ptp4l401ktimersoftd/308:51:483
152502780,3sleep00-21swapper/010:45:240
152502780,3sleep00-21swapper/010:45:230
11450997642,4cyclictest9-21ksoftirqd/007:20:300
11450997568,4cyclictest9-21ksoftirqd/008:20:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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